Two-Level Adiabatic Logic (2LAL)

Retractile cascades and SCRL proved fully adiabatic silicon was possible — but they are baroque: stacks of rail sequences, forward blocks paired with inverse blocks, timing disciplines with the fragility of a soufflé. In the early 2000s Michael Frank asked the minimalist's question: what is the simplest circuit style that keeps all the fully-adiabatic rules? His answer, Two-Level Adiabatic Logic (2LAL), is almost embarrassingly spare: nothing but CMOS transmission gates, driven by four trapezoidal clocks, wired so that data marches down a pipeline like a shift register — and nothing is ever erased in place.

Four clocks, ninety degrees apart

Everything in 2LAL dances to four periodic supply waveforms, \phi_0, \phi_1, \phi_2, \phi_3, each a trapezoid — ramp up for a quarter-period, hold high ("shelved") for a quarter, ramp down for a quarter, hold low for a quarter — and each shifted a quarter-period (90°) after the one before. "Two-level" names the shape: the waveform only ever rests at the two logic levels, 0 and V, moving between them exclusively by gentle ramps. The ramps are the adiabatic charging events; the shelves are when neighbours sample.

Because the clocks are the power supply, every charging current in the whole chip flows from a ramping source — there is no fixed rail anywhere in the logic to slam a capacitor against. The ½CV² habit is not resisted; it is architecturally impossible.

A pipeline that copies, then un-copies

A 2LAL pipeline is a chain of latch stages, stage i clocked by \phi_{i \bmod 4}. Each tick of a quarter-period, one thing happens per stage, and it is always one of two reversible moves:

Copy forward: as its clock ramps up, a stage's transmission gates — steered by the data held in the stage before — charge its output nodes adiabatically. The stage now holds a copy of (a logic function of) its predecessor's data.
Un-copy behind: one tick later, the predecessor's clock ramps down, and the predecessor's nodes are gently retracted — steered by the copy now living safely downstream. The stale value is un-computed, its charge handed back to the clock.

So data marches forward like a wave, each value existing in two adjacent stages for one overlapping beat — copied ahead, then retracted behind. It is a shift register of reversible latches: at no moment is any node overwritten while it still holds the only copy of anything. The old value does not die; it backs out of the room. Logic comes almost for free: make the "copy" a controlled connection — transmission gates arranged so what is passed forward is a reversible function of several upstream signals — and the shift register computes as it marches.

built from CMOS transmission gates only, powered directly by four trapezoidal clock phases \phi_0\ldots\phi_3 at 90° offsets;
each pipeline stage copies its data forward on its clock's up-ramp, and is un-copied (retracted) on the down-ramp once the copy is safe downstream — nothing is ever erased in place;
in simulation its dissipation per operation falls with clock slowing to astonishing depths — approaching the ~1 eV scale, thousands of times below conventional CMOS switching energies of order 10^{4}–10^{5} eV.

Those simulated numbers deserve their caveats — ideal switches, patient clocks, leakage set aside — but the order of magnitude is the message: with nothing exotic, just transmission gates and choreography, the switching-energy ladder from the start of this module can be descended almost to the rungs where kT physics begins.

The humblest circuit in CMOS: an nMOS and a pMOS transistor in parallel, gates driven by opposite control signals, forming a switch that either connects two nodes or doesn't. Unlike a lone nMOS (which passes a strong 0 but a degraded 1) or a lone pMOS (the reverse), the pair passes both levels cleanly — essential here, because an adiabatic circuit must track a ramp faithfully all the way from 0 to V without ever leaving a stranded voltage gap across a switch. Notice also what a transmission gate is not: it has no preferred direction. Charge flows through it equally happily either way — a little two-way valve, reversible right down in the device physics. It is the natural atom for a logic style whose every move must be retraceable.

A hasty reading — "the predecessor's value gets removed each tick" — makes 2LAL sound like it erases constantly, which would put Landauer's toll on every stage. Look closer at the order of events. The un-copy happens while the forward copy exists, and it is steered by that copy (or by the still-held upstream data): the charge is guided back out along the path that put it in. That is un-computation — a bijective step with the information preserved downstream — not a blind reset. The same idea at the level of whole computations is Bennett's compute–copy–uncompute trick; 2LAL runs it at the level of single latch ticks, millions of times a second. The discipline to watch is only this: a value may be retracted only after its successor stage has taken its copy — break that overlap and the retraction has nothing to steer it, and honest erasure (with its bill) sneaks back in.