Retractile Cascades and SCRL

The previous lesson laid down the law: fully adiabatic operation means never switching under bias, never abandoning charge, and being able to retrace every state change — which forces the logic to be reversible. Fine words. But can you actually wire them? This lesson meets the two historic architectures that first said yes: Storrs Hall's retractile cascade (1992) and Younis and Knight's Split-level Charge Recovery Logic (SCRL) from MIT. Both are blueprints for computing forwards and then carefully un-computing backwards, entirely in transistors — reversibility made concrete in silicon.

The retractile idea: compute like nested parentheses

Picture a chain of logic stages 1, 2, …, n, each computing from the outputs of the one before. A retractile cascade runs them like this:

Charge phase: ramp stage 1's outputs up (adiabatically, from its held inputs); then stage 2's; then stage 3's; … up to stage n. The answer is now available at the end of the chain — read it, or copy it out reversibly.
Retract phase: now un-drive everything in reverse order: stage n retracts first, then n-1, …, and stage 1 retracts last. Each retraction ramps the stage's outputs back down along the same path that charged them, returning the charge to the supply.

The crucial discipline: a stage's inputs must be held steady until its outputs have retracted. Stage 2 can only be un-driven gently while stage 1's outputs — the very signals that determined stage 2's values — are still present to steer the charge back out. So stage 1, which charged first, must stand guard the longest and retract last. Write charging as an opening bracket and retraction as a closing one and the timeline reads (\,_1(\,_2(\,_3\;)\,_3)\,_2)\,_1 — perfectly nested parentheses, never crossing.

The timeline, drawn

Step through the figure: each bar shows one stage's output voltage over the six phases of a three-stage cascade — ramp up, hold, ramp back down. Watch how the intervals nest: the earlier a stage charges, the later it retracts.

The cost of the discipline is easy to read off: with n stages the full cascade takes 2n phases, and early stages hold their outputs for almost the entire time. Deep logic means long holds, and every held node leaks all the while — one more reason the leakage floor from the previous lesson matters.

SCRL: split rails that breathe

Retractile cascades gate their logic; SCRL instead choreographs its power rails. In Split-level Charge Recovery Logic every node idles at the neutral mid-level V/2. To compute, the two supply rails of each stage split apart — ramping gradually from V/2 out to V and 0 — and the stage's pass-gate logic steers each output node up or down according to its inputs. Stages are driven by a sequence of such rail pairs, so a wave of "rail-splitting" sweeps down the pipeline. To un-compute, the whole rail sequence plays in reverse: the rails squeeze back together to V/2, gently pulling every output node back to neutral and returning its charge to the supply.

And here is the reversibility requirement made physical. Squeezing the rails back together only recovers the charge adiabatically if, at that moment, the circuit can still steer each node back along the path it came — which requires the inverse of the logic function to be available to un-drive the nodes. SCRL pipelines are therefore built from forward blocks paired with inverse blocks; feed-forward logic whose inverse cannot be formed simply cannot be retracted without breaking the no-switching-under-bias rule. What Landauer argued with entropy, the rail sequence enforces with volts.

Retractile cascade (Hall, 1992): stages charge in order 1, 2, \ldots, n and retract in reverse order n, \ldots, 2, 1; inputs are held until their outputs retract, so the active intervals nest like parentheses; the whole cycle spans 2n phases;
SCRL (Younis–Knight): rails split from V/2 outward to drive pass-gate logic, then reverse their sequence to reclaim the charge;
both need the logic's inverse available to un-drive nodes — logical reversibility is a wiring requirement, not a philosophical preference.

SCRL was not a paper exercise. In the mid-1990s Tom Knight's group at the MIT AI Lab — Saed Younis, and soon Carlin Vieri, Michael Frank and others — built the Pendulum project around it, named for the physicist's favourite example of a system that swings back and forth losing almost nothing. The group fabricated real SCRL test chips, and the project grew a full ecosystem: energy-recovering supplies, reversible logic synthesis, and eventually a complete reversible processor architecture (a story two lessons from now). Their design rule-of-thumb has outlived the hardware: every violation of full adiabaticity in a "charge recovery" circuit can be found by asking where would this energy go if I clocked it infinitely slowly? — the same audit you learned last lesson, invented under deadline pressure by graduate students with an oscilloscope.

It is tempting to gloss "stage 3 retracts" as "stage 3's result is erased" — and then to panic, because erasure costs kT \ln 2. But retraction is the opposite of erasure. An erased node is forced to a standard level regardless of what it held — a two-states-to-one squeeze, information destroyed. A retracted node is ramped back to neutral using the very inputs that computed it, still held next door: the information is not destroyed but un-computed, its charge banked back in the supply, the whole move invertible at every instant. That is also why the ordering rule is unbreakable: retract stage 1 before stage 2 and you have destroyed the inputs stage 2 needs for its own gentle retraction — its nodes must then be reset blind, which is erasure, with the bill to match.