Open the research literature and you will find a zoo of "adiabatic logic families" — dozens of circuit styles, each with its own acronym, each promising to ride the ramping-supply trick down to negligible energy. Here is the uncomfortable secret: most of them can't. Slow their clocks a hundredfold and the energy per operation stops falling, stuck on a floor thousands of times above where the theory says it could go. These are the quasi-adiabatic families. Understanding exactly where they cheat is the best diagnostic skill in this field — and it leads to a beautiful punchline: a circuit that commits none of the sins is forced, by that very discipline, to be logically reversible.

The three classic sins

A circuit is only as adiabatic as its worst habit. Each of these habits burns a chunk of energy that is fixed per cycle — no amount of slowing shrinks it:

• Charging through a diode. Many families steer charge with diodes (or diode-connected transistors) because it makes the logic simple. But a diode conducts only by dropping a roughly fixed voltage V_d (about half a volt) across itself. Every coulomb that passes pays it: moving charge Q = CV through the diode burns E = QV_d = CV\,V_d per cycle — independent of the ramp time. Slowing the clock spreads the same toll over more time; it never reduces it.
• Switching a transistor while the voltage across it is nonzero. Turn a switch on with a potential difference V_x still sitting across it, and the connected capacitance snaps the rest of the way — a miniature fixed-rail event burning about \tfrac{1}{2}CV_x^2. This is the non-adiabatic residue, and it hides in circuits that look innocent on paper.
• Abandoning charge to ground. Any node that gets discharged into ground instead of being ramped back into the supply donates its stored \tfrac{1}{2}CV^2 straight to the heatsink.

A family with any of these habits is quasi-adiabatic: its energy per cycle looks like E = \tfrac{RC}{T}CV^2 + E_{\text{fixed}}, and once T is large the fixed term rules.

The leakage floor and the U-curve

Even a circuit with no fixed-loss sins hits a subtler wall. Real transistors leak: a small current I_{\text{leak}} seeps through nominally-off devices the whole time the circuit is powered. Leakage energy grows with the cycle time, so the total is

a U-shaped curve with a genuine minimum at a finite optimal ramp time. Balance the two terms and the optimum sits where they are equal — beyond it, patience actively hurts. Slide the leakage up and watch the whole floor rise and the sweet spot move earlier:

In these normalised units (adiabatic term a/T, leakage term LT) the optimum is T^{*} = \sqrt{a/L}, and the minimum energy is E_{\min} = 2\sqrt{aL} — both terms contributing equally. Quadruple the leakage and the best ramp time halves while the floor doubles. Leakage is why practical adiabatic circuits favour slightly old-fashioned, low-leak transistor processes over the leakiest bleeding-edge nodes.

Fully adiabatic — and the trap that closes

Call a circuit fully adiabatic when it commits none of the fixed-loss sins. Spelled out as design rules:

• never switch a transistor while a nonzero voltage sits across it;
• never let charge flow to ground or through a diode drop — every electron is escorted back to the supply;
• therefore every state change must be undoable along the path that made it — the circuit must be able to retrace each charging step in reverse.

Now watch the trap close. To un-drive a node adiabatically, the circuit must, at un-driving time, still be able to determine that node's value from signals it still holds — otherwise it cannot line the voltages up before reconnecting, and rule one is violated. A gate that has thrown away the information needed to reconstruct its outputs simply cannot take them back gently. Chasing a purely electrical goal — zero fixed losses — has forced a logical property: fully adiabatic circuits must be logically reversible. The two halves of this course collide in a transistor diagram.

And the converse cuts just as hard: a quasi-adiabatic family that erases bits is bounded below by Landauer's principle — at least kT \ln 2 per erased bit, no matter how slowly it is clocked, on top of all its engineering losses. Erasure is not an engineering bug you can ramp away; it is a physics invoice.