Power Clocks and Resonant Supplies

Time to face the elephant in the module. Every adiabatic family we have met — 2LAL, SCRL, the retractile cascades — computes its energy books on one enormous assumption: that something, somewhere generates those beautiful trapezoidal ramps, absorbs the charge the logic hands back, and does it all without waste. That something is called the power clock, because it is simultaneously the chip's clock and its power supply. Adiabatic logic did not eliminate the dissipation problem — it relocated it, out of the logic and into the supply. If the supply generates ramps the brute-force way, every joule saved in the gates is burned in the generator, and the whole enterprise is bookkeeping theatre.

Resonance: let physics make the ramp

The escape is old, elegant physics: resonance. Connect an inductor L across the logic's capacitance C — and note the delicious trick: the logic's own node capacitance is the tank's C. The pair forms an LC oscillator: energy sloshes back and forth between the capacitor's electric field (nodes charged, logic "high") and the inductor's magnetic field (nodes empty, current flowing), swinging at the natural frequency \omega = 1/\sqrt{LC}. Nobody "generates" the down-ramp and "absorbs" the returning charge — the oscillation is the charge leaving and returning, the electrical twin of a pendulum trading height for speed. The supply only needs to top up what friction skims off each swing.

How much is skimmed? That is measured by the resonator's quality factor Q — roughly, how many swings it takes to ring down. Per cycle, a resonant supply loses a fraction of the circulating energy on the order of \pi/2Q (take the constant as folklore; the scaling 1/Q is what matters). So:

\text{loss per cycle} \;\sim\; \frac{\pi}{2Q}, \qquad Q = 1000 \;\Rightarrow\; \text{about } 0.16\% \text{ lost — } 99.8\% \text{ recovered.}

The chart makes the design pressure vivid: at Q = 10 the tank bleeds out in a few dozen cycles, while at Q in the hundreds it barely notices. The real efficiency of an "adiabatic" chip is set here, in the supply's Q, at least as much as in the logic family.

Sine vs trapezoid — and other ways to make a ramp

There is a shape problem, though. An LC tank naturally produces a sine wave; 2LAL's choreography wants a trapezoid, with flat shelves for neighbours to sample. The engineering menu is a set of compromises:

Accept the sine. Redesign the logic timing to tolerate rounded tops; you keep the tank's simplicity and pay a small non-ideality in the logic.
Stepwise (staircase) charging. Approximate the ramp as n small voltage steps served from a bank of tank capacitors at intermediate voltages. Each step is a little fixed-rail event, but at only V/n a step the total falls to about \tfrac{1}{2}CV^2/n — an n-fold saving that approaches a true ramp as n grows.
MEMS resonators. Replace the electrical inductor with a vibrating micromechanical element. Mechanical resonance on chip-compatible scales reaches Q in the thousands to tens of thousands — far beyond on-chip inductors, whose Q languishes in the tens — at the price of fixed frequency and delicate coupling.

adiabatic logic shifts the dissipation problem into the supply: the power clock must generate ramps and reabsorb returned charge;
resonant supplies (LC tanks — with the logic capacitance as the C — stepwise tank-capacitor ladders, MEMS resonators) recycle the sloshing energy, losing a fraction \sim \pi/2Q per cycle;
the system's true energy per operation is logic loss + supply loss — the quality factor Q is as decisive as the logic family.

Strike a bronze bell and it hums for ten seconds or more: tens of thousands of vibration cycles from one strike. That is Q made audible — a bell is a mechanical resonator with Q in the tens of thousands, losing only a hair of its energy per swing. A wine glass rings similarly; a lump of clay (Q \approx 1) lands with a thud, all its energy gone in one "cycle". Quartz watch crystals sit near Q \sim 10^5, which is why a microscopic sliver of quartz can tick for a year on a coin cell. The dream of the resonant power clock is exactly this: make the computer's supply a well-struck bell, so the energy of every clock swing rings on and on through billions of cycles, merely borrowed by the logic on each pass — never spent.

Here is the oldest trap in adiabatic computing, and referees still catch it: a paper simulates the logic alone, drives it from an ideal mathematical ramp, integrates the tiny I^2R loss in the transistors, and announces near-zero-energy computing. But an ideal ramp is not free — someone must build the generator, and a generator made of ordinary switching converters can easily burn more than the logic saves. The honest ledger is always the whole system: logic dissipation plus everything lost in the power clock, its resonator, and its control circuitry. A claim of "zero-energy logic" powered by an unexamined clock generator is exactly as convincing as a perpetual-motion machine powered by a wall socket that is out of frame. When you read any energy claim — in this field or elsewhere — first ask: where is the boundary of the system being billed?