Adiabatic Switching

Fill a glass under a tap opened full blast and half the water ends up on your shoes. Open the tap gently and almost every drop lands in the glass. The previous lesson showed that CMOS fills its capacitors under a full-blast tap: connect the node straight to the fixed rail and exactly half the energy — \tfrac{1}{2}CV^2 — splashes away as heat, no matter what the resistance is. The waste was baked into the method, not the components.

So change the method. Adiabatic switching charges the capacitor from a supply whose voltage ramps up slowly, so the node is never far below the rail feeding it. The loss stops being a fixed \tfrac{1}{2}CV^2 and becomes a quantity you can make as small as you like — by taking longer. It is the single most important circuit idea in this module, and it is the direct engineering echo of a thermodynamic truth this course keeps meeting: gentle, quasi-static processes can approach zero dissipation.

The ramp calculation

Replace the fixed rail with a supply that ramps linearly from 0 to V over a time T. The capacitor voltage tracks the ramp, lagging just enough to drive the charging current through the resistance R. The current is nearly constant:

I \;\approx\; \frac{Q}{T} \;=\; \frac{CV}{T}.

The heat burned in the resistor over the whole ramp is then

E_{\text{diss}} \;=\; I^2 R\, T \;=\; \left(\frac{CV}{T}\right)^{\!2} R\,T \;=\; \frac{RC}{T}\cdot CV^2.

Look at the prefactor. RC is the circuit's natural charging time — a few picoseconds for a logic gate. If you ramp over exactly T = RC, you burn the full CV^2 (worse than conventional!). Ramp ten times slower and you burn a tenth as much. Ramp a thousand times slower and the loss is a thousandth of CV^2. There is no floor in this formula: E_{\text{diss}} \to 0 as T \to \infty.

charging C to V through resistance R from a supply ramping over time T \gg RC dissipates E \approx \dfrac{RC}{T}\,CV^2 — vanishing as T grows;
"adiabatic" means the ramp is gentle enough that the voltage across the resistance stays small at every instant, so almost no power is ever being burned;
the energy must also be recovered: ramp the supply back down and the charge flows back into it. Dumping the node to ground instead throws away the stored \tfrac{1}{2}CV^2 — and with it the whole advantage;
the price of low dissipation is time: energy per operation trades directly against speed.

See the trade

The chart plots the adiabatic loss (RC/T)\,CV^2 against ramp time T, for a normalised gate with CV^2 = 1\ \mathrm{fJ} (about C = 1\ \mathrm{fF} at V = 1\ \mathrm{V}). The flat line is the conventional fixed-rail loss \tfrac{1}{2}CV^2, which no amount of patience changes. Slide RC to see the crossover move: the adiabatic curve dips below the conventional line exactly at T = 2RC, and keeps falling forever.

Worked numbers: a gate with R = 10\ \mathrm{k\Omega} and C = 1\ \mathrm{fF} has RC = 10\ \mathrm{ps}. Ramp it over T = 1\ \mathrm{ns} — a hundred time-constants — and the loss is \tfrac{RC}{T} = 0.01 of CV^2: fifty times less than the conventional \tfrac{1}{2}CV^2, at a gate speed a modern chip would find leisurely but not absurd. Ramp over 100 ns and you are five thousand times below conventional. Slow is the feature.

The catch: you must give the charge back

Halfway through a cycle, the node sits at V holding \tfrac{1}{2}CV^2 of energy. In conventional CMOS the story ends with an nMOS transistor dumping that charge to ground — the stored energy becomes heat, full stop. An adiabatic circuit must not do this. Instead the supply ramps back down, and the charge flows gently out of the capacitor and back into the supply, again losing only (RC/T)\,CV^2 on the way. Energy is borrowed, used to represent a logic level for a while, and returned — like a library book, not a firework.

This is where the subject earns its place in a reversible-computing course. A supply that can reclaim charge must run its waveform backwards; a circuit whose every node can be un-driven must know how to retrace its steps. Asymptotically zero dissipation per operation is on offer — but only for machinery that never throws anything away, physically or logically. The next lessons make that connection exact.

In physics, an adiabatic process is one gentle enough that the system stays arbitrarily close to equilibrium the whole way — compress a gas infinitely slowly and you can recover every joule you put in. Electrical engineers borrowed the word for exactly that reason: a slow ramp keeps the capacitor's voltage arbitrarily close to the supply's, so the system is never far from its electrical equilibrium and almost nothing is irreversibly lost. (Pedants note the borrowing is slightly loose — the Greek roots mean "no heat passes through", and here a little heat always does. The community shrugged and kept the name.) The deep point stands: dissipation is the price of hurry. The thermodynamic limit of zero loss at zero speed reappears, transistor for piston, in a silicon circuit.

The formula (RC/T)\,CV^2 promises that patience conquers all: double T, halve the loss, forever. Real transistors break the promise. Every device leaks — a small current trickles through even when a transistor is nominally off — and leakage burns energy in proportion to how long the cycle lasts. Stretch T and the switching loss falls but the leakage bill grows, so the total energy per operation is U-shaped in T, with a sweet-spot ramp time and a floor set by the leak. The next lesson draws that U-curve — and catalogues the other, sneakier ways supposedly "adiabatic" circuits quietly burn fixed chunks of energy that no slowness can shrink.