The Electronic–Photonic Interface
Module 5 left us with a genuinely startling number: a photonic mesh can perform a
multiply-accumulate for a few femtojoules of light — orders of magnitude below what a digital
multiplier pays. This module is about why that number, alone, builds nothing. A photonic
processor is an analog island in a digital sea. The activations arrive as bits
in SRAM; the results must return as bits to a CPU that has never heard of a phase shifter. Every
number therefore crosses a border twice: a digital-to-analog converter (DAC)
turns bits into a drive voltage on the way in, and a photodetector, amplifier and
analog-to-digital converter (ADC) turn optical power back into bits on the way
out. Each crossing costs energy — and the toll at the border is often hundreds of times
the cost of the journey through the country. The
noise
and precision lesson showed that analog optics is honest only to a handful of bits;
this lesson shows that even those few bits are expensive to import and export. Systems thinking
about photonic computing starts here, at the interface, because this is where real energy
budgets are won and lost.
The price of a conversion
Data converters are a mature, brutally competitive field, and their state of the art is tracked
in long-running public surveys (Walden's, continued by Murmann). The headline metric is the
Walden figure of merit: take a converter's power P,
divide by its sample rate f_s and by the number of distinguishable
levels it actually resolves, 2^{\mathrm{ENOB}} (ENOB = effective
number of bits, always below the marketing bits):
\mathrm{FOM_W} \;=\; \frac{P}{2^{\mathrm{ENOB}}\, f_s}
\qquad\Longrightarrow\qquad
E_{\text{sample}} \;=\; \mathrm{FOM_W}\cdot 2^{\mathrm{ENOB}} .
- energy per sample is E = \mathrm{FOM_W}\cdot 2^{B} —
exponential in the bit-depth B, linear in
nothing;
- in the technology-limited (Walden) regime, each extra bit costs
2\times the energy; good GHz-class converters sit around
\mathrm{FOM_W} \approx 5\text{–}50 fJ per conversion-step;
- in the thermal-noise-limited (Schreier) regime — which takes over at high
resolution — halving the quantisation noise voltage requires quadrupling the sampling
capacitance (the kT/C noise floor), so each extra bit costs
4\times;
- these are survey envelopes over thousands of published chips, not theory — but they have
moved slowly for decades, and no photonics roadmap gets to assume they will vanish.
Put numbers in. An 8-bit converter at \mathrm{FOM_W} = 10 fJ/step
costs 10 \times 256 \approx 2.6 picojoules per sample;
at 10 GS/s that is 26 mW of continuous power — per converter, and a mesh needs one per channel.
Compare the femtojoule-scale optical MAC and the mismatch is stark: the doorman charges a
thousand times the price of the show. The chart shows both scaling laws; slide the figure of
merit to see how much (or little) better converters would have to get.
Drivers and receivers: the rest of the border post
The DAC and ADC are the biggest line items, but not the only ones. On the way in, the DAC's
output must actually swing a
modulator:
a driver charges the modulator's capacitance C
through a voltage swing V, paying of order
\tfrac{1}{4}CV^2 per symbol — with
C \approx 100 fF and V \approx 2 V, about
100 fJ, and often several times that once the amplifier's own quiescent power is charged to the
account. On the way out, a photodiode delivers microamps of photocurrent, far too feeble for any
ADC; a transimpedance amplifier (TIA) converts current to voltage with enough
gain and bandwidth to hand the ADC a clean signal, at a cost of hundreds of femtojoules to a
picojoule per sample (the receiver chain from the
photodetectors
lesson). None of these stages does arithmetic. They are pure overhead — the customs
paperwork of the analog border — and in published photonic accelerator prototypes they routinely
outweigh the optics by one to two orders of magnitude.
Amortisation: divide the toll by N
Here is the saving grace, and it is structural. In an N \times N mesh
performing a
matrix–vector
multiply, one converted input sample fans out to N
multiply-accumulates, and one output sample carries the sum of N of
them. The conversion energy per MAC is therefore
E_{\text{conv/MAC}}
\;=\; \frac{E_{\mathrm{DAC}} + E_{\mathrm{ADC}}}{N},
and the whole economic case for photonic computing hides in that denominator. With
E_{\mathrm{DAC}} = E_{\mathrm{ADC}} = 2.6 pJ and
N = 64, conversion charges 80 fJ to every MAC — already level with a
good electronic accelerator before the optics has done anything. At
N = 512 the toll drops to 10 fJ and light starts to win. Run the
arithmetic yourself:
const fom = 10; // converter figure of merit, fJ per conversion-step
const bits = 8; // resolution of DAC and ADC
const eOpticalMac = 5; // fJ per MAC for the light itself (Module 5's number)
const eElectronicMac = 100; // fJ per MAC, competitive digital INT8 accelerator
const ePerSample = fom * Math.pow(2, bits);
console.log("energy per conversion: " + ePerSample + " fJ (" + bits + " bits)");
console.log("");
console.log("N conv/MAC total/MAC");
for (const N of [8, 16, 32, 64, 128, 256, 512]) {
const conv = (2 * ePerSample) / N; // one DAC + one ADC sample per N MACs
const total = conv + eOpticalMac;
const verdict = total < eElectronicMac ? " ← beats electronics" : "";
console.log(
String(N).padEnd(8) +
(conv.toFixed(1) + " fJ").padEnd(13) +
(total.toFixed(1) + " fJ").padEnd(10) + verdict,
);
}
Beyond growing N, three further amortisation levers recur in every
serious design. Weight reuse: program the mesh once per layer and stream
thousands of activation vectors through it, so the weight-side DACs are charged per layer, not
per sample. Batching: the same idea on the activation side — the fixed costs of
a pass are shared across a batch. And staying analog longer: if the output of
one optical layer can feed the next without a detect–digitise–redrive round trip, two whole
border crossings vanish per layer. That last lever is the sharpest and the most dangerous, as the
vignette below explains.
The thermal limit is worth deriving once, because it is physics rather than engineering
fashion. Any voltage sampled onto a capacitor C carries an
irreducible thermal noise of variance kT/C — the resistor that
charged it hands over Johnson noise, and equipartition leaves \tfrac12 kT
of energy rattling in the capacitor no matter how good the circuit is. To add one bit of
resolution you must halve the quantisation step, which means halving the tolerable noise
voltage, which means quartering the noise power — and the only knob is
C \to 4C. A four-times-larger capacitor takes four times the charge,
and therefore four times the energy, to swing. That is the 4^B wall,
and it is why 12-bit gigasample converters are power-hungry monsters while 4-bit ones are almost
free. Note the family resemblance to the argument in the
energy-cost-of-signalling
lesson: analog precision, wherever it lives, is billed against
kT — the same thermodynamic ledger that runs all of computing's
accounts.
The classic error — committed in good faith in many early photonic-computing papers, and in
rather less good faith in some marketing decks — is to quote the energy of the optical
MAC and quietly leave the converters off the bill. "Sub-femtojoule per operation" is a true
statement about the light and a false statement about the system. The honest accounting is the
amortised sum: optics plus (E_{\mathrm{DAC}}+E_{\mathrm{ADC}})/N
plus driver, TIA, laser wall-plug and control — at which point many published systems
land within a factor of a few of a well-designed digital chip, not a factor of a thousand ahead.
When you read any per-op energy claim for an analog accelerator, your first question should be a
reflex by the end of this module: who paid for the conversions? If the paper doesn't
say, assume the answer is "nobody yet". The
benchmarking
lesson turns this reflex into a full checklist.
Staying analog longer — and its price
The most aggressive amortisation strategy deserves its own caution. Chaining optical layers
without intermediate digitisation removes conversions, but it also removes the one thing digital
systems get for free: signal restoration. A digital gate snaps every value back
to a clean 0 or 1; an analog chain lets noise, crosstalk and calibration error
accumulate stage after stage, exactly as the
precision
lesson quantified. Deep learning offers a genuine escape hatch here:
mixed-precision
training has shown that networks tolerate — even train happily at — 8, 6, sometimes
4 bits. Every bit you can shave saves 2\times to
4\times on every conversion and relaxes the analog chain's noise
budget at the same time. Co-designing the algorithm's precision appetite with the interface's
exponential price list is the subject of the
co-design
lesson; first, though, the
next
lesson confronts an even less glamorous tax: the electrical cost of simply holding
an analog processor still.