Co-Packaged Optics

Follow one bit out of a 51.2 Tb/s switch ASIC. It leaves the die on an electrical SerDes lane at 200 Gb/s PAM4, fights its way down twenty centimetres of printed circuit board — through vias, connector stubs and 30-odd dB of copper loss, kept alive by a DSP retimer — and finally reaches the faceplate, where a pluggable transceiver converts it to light for the easy part of its journey. Now the absurdity: that last electrical sprint to the faceplate can burn more energy per bit than the ten optical kilometres that follow. On a fully loaded switch, 64 pluggables at ~15 W each plus the long-reach SerDes to feed them consume on the order of a kilowatt — comparable to the switching ASIC itself. The interconnect bottleneck has retreated from the network into the box.

Co-packaged optics (CPO) is the blunt fix: stop hauling multi-hundred-gigabit electrical signals across the board at all. Lift the optics out of the faceplate and set them down on the package substrate, millimetres from the ASIC — the same logic that pushed chiplets into mainstream silicon: when the wire is the problem, shrink the wire.

Two floor plans

The whole idea fits in one picture. Same board, same faceplate — the only question is where the electrical signalling ends:

Shrinking the electrical reach from ~20 cm to ~2 mm changes the SerDes species entirely. The long-reach (LR) lane needs heavy equalization and a DSP against ~30 dB of channel loss — roughly 5–6 pJ/bit at each end, plus a retimer in the middle. The die-to-engine hop is an extra-short-reach (XSR) or die-to-die link over a nearly lossless channel: ~1 pJ/bit, no retimer, no DSP. The channel got easy, so the electronics got cheap — the same lesson as the previous two lessons, now applied inside the package.

The arithmetic of moving in

Put numbers on the two floor plans, per bit and then per box. A pluggable path costs roughly: LR SerDes 5 pJ/b, retimer 3 pJ/b, module's own DSP and optics 7 pJ/b — call it \sim 15 pJ/b. A co-packaged path: XSR SerDes 1 pJ/b, engine optics 4 pJ/b — call it \sim 5 pJ/b. At the full 51.2 Tb/s:

(15 - 5)\ \text{pJ/b} \times 51.2\ \text{Tb/s} \;=\; 512\ \text{W}

— half a kilowatt saved per switch, which at datacenter scale is megawatts, and (since a pJ/b at 10⁻¹² J times Tb/s at 10¹² b/s is exactly a watt) an arithmetic you can do on your fingers. Check it, and the package-shoreline claim, in code:

const rateTbs = 51.2; const pluggablePjPerBit = 5 + 3 + 7; // LR SerDes + retimer + module DSP/optics const cpoPjPerBit = 1 + 4; // XSR SerDes + on-package engine // pJ/b × Tb/s = W (1e-12 J/b × 1e12 b/s) console.log("pluggable path: " + pluggablePjPerBit * rateTbs + " W"); console.log("co-packaged: " + cpoPjPerBit * rateTbs + " W"); console.log("saved per box: " + (pluggablePjPerBit - cpoPjPerBit) * rateTbs + " W"); // Shoreline: the package is a bigger island than the die. const dieEdgeMm = 25, packageEdgeMm = 75; const engineTbs = 6.4; // one optical engine const enginePitchMm = 9; // engine width along the package edge const engines = Math.floor((4 * packageEdgeMm) / enginePitchMm); console.log("die shoreline: " + 4 * dieEdgeMm + " mm; package shoreline: " + 4 * packageEdgeMm + " mm"); console.log("engines that fit: " + engines + " -> " + engines * engineTbs + " Tb/s of optical escape");

The second half of that output answers the beachfront problem from lesson one: the package perimeter is three times the die's, and each optical engine escapes multiple terabits through a fibre ribbon a few millimetres wide. A faceplate holds ~32–36 pluggable cages and is itself a shoreline — at 800G each, about 25–30 Tb/s of front-panel ceiling. CPO sidesteps it: fibre connectors pack far denser than QSFP cages, because glass needs no cage, no heatsink and no 15 W of cooling airflow per port.

Chiplets that speak light

Mechanically, a co-packaged optical engine is just another chiplet: a silicon-photonics die (plus its driver/TIA electronics) mounted on the same substrate or interposer as the big digital die, talking to it over the same class of short-reach die-to-die links that already stitch multi-die packages together. That framing matters because it makes photonics composable: the same engine that rings a switch ASIC can ring a GPU. And GPUs are the hungriest customers in sight — scale-up fabrics like NVLink already push terabytes per second per device through copper that tops out at a couple of metres' reach, hard against exactly the wall this module started with. Optical engines on the GPU package promise to blow the scale-up domain past the rack — a thread we pick up properly in the final lesson.

It is tempting to read CPO as "optics finally wins, electronics retreats". Look closer: every photon in a CPO system still begins and ends its life as electrons, and the E/O conversion toll from lesson one is still charged in full — CPO shrinks the electrical leg, it doesn't abolish it. Meanwhile two problems get harder. Thermal: the engines now live centimetres from a 500 W ASIC, and photonic devices — especially microrings — drift with every degree. Serviceability: a failed pluggable is swapped in thirty seconds by a technician with cold coffee; a failed co-packaged engine is soldered to a $20,000 board. Real CPO designs answer with remote, field-replaceable laser modules, redundant lanes, and a lot of burn-in testing — engineering nobody needed while the optics lived in a socket. Every integration in computing history has run this same ledger: performance and energy versus modularity and repair. CPO is simply the photonic instalment.

In most CPO designs, one component conspicuously refuses to move into the package: the laser. Instead an external laser source — its own little pluggable module at the faceplate — pumps continuous-wave light through polarization-maintaining fibre into the package, where the modulators do the actual work. Three reasons, all endearingly unglamorous. Lasers hate heat: their efficiency and lifetime degrade steeply with temperature, and beside a half-kilowatt ASIC is the worst seat in the house. Lasers die first: they are the least-reliable device in the whole chain, so you want them where a technician can swap one — the pluggable's one great virtue, retained for exactly the component that needs it. And lasers are shareable: one good external source can feed many modulators through splitters, amortising its cost and letting the photonic dies be all-silicon (silicon famously being a hopeless laser material, as Module 3's laser lesson lamented). The result is a neat division of labour: light is generated where it can be cooled and replaced, and put to work where the bits are.

Where this goes next

CPO moves the E/O boundary to the package rim; the bits themselves still change into electrons at every switch hop to be buffered, scheduled and routed. The obvious next question: could the switching itself happen in the optical domain, so a bit stays light from source to destination? That is the promise — and the sharply limited fine print — of optical switching fabrics, next.