Digital electronics offers two ways to get a chip: design an ASIC — years, millions of dollars,
one function forever — or buy an FPGA, whose
The building block is the tunable basic unit (TBU): a
The crucial structural difference from the
Suppose each TBU is
A delay line. Set twenty TBUs along a snaking path to bar state:
programmable in ~4 ps steps by lengthening or shortening the snake — the tapped, adjustable delay that microwave photonics and beamforming systems pay dearly for as custom chips.
A ring resonator. Close the six TBUs around one hexagonal cell into a loop:
perimeter
with the coupling into the loop — which sets the filter's sharpness — dialled by the partial state of one boundary TBU. Merge two cells into a twelve-TBU loop and the FSR halves: resonator size is a software parameter.
An interferometer. Split light along two different mesh paths and recombine it, and you have synthesized an unbalanced MZI whose path imbalance — hence filter period — is chosen in units of whole TBUs. The published demonstrations (Pérez et al., 2017, on a seven-cell hexagonal mesh) ran through over twenty distinct circuits on one chip: FIR and IIR filters, delay lines, splitters, and simultaneous independent functions on different corners of the same fabric.
Once the hardware is generic, the intelligence moves into software, and the field borrows its vocabulary wholesale from electronics: a netlist (the circuit you want), a place-and-route step (graph algorithms mapping it onto healthy, unoccupied TBUs), a bitstream (the vector of phase settings driven onto the chip). The fabric even supports the photonic version of self-test: built-in monitor photodiodes let control loops discover each TBU's actual calibration, route around defective units, and hold circuits on target as the chip drifts thermally — David Miller's self-configuring mesh ideas put to work. This is why the field calls itself software-defined photonics: the deliverable is not a chip but a chip plus a compiler.
Frontier accounting, as ever. Demonstrated: university and startup fabrics of tens of cells (the field's first commercial general-purpose processor, iPronics' SmartLight, shipped from the Valencia group's work), reprogrammed in milliseconds among dozens of RF-photonic functions. Speculative: the thousand-cell fabrics that would make "FPGA of light" literally true — blocked today by accumulated loss, by the electrical I/O of driving thousands of phase shifters, and by the control software's scaling.
A mesh cell could be triangular, square or hexagonal — the three regular tilings of the plane — and the choice was a genuine research question. Triangles give the shortest possible loops (three TBUs), hence the largest synthesizable FSR, but their sharp 60° bends are unkind to waveguides and their routing options tangle quickly. Squares are tidy but support fewer distinct path lengths per area. The Valencia group's analysis (Pérez, Capmany et al.) found the hexagonal lattice the sweet spot: gentle 120° junctions, the richest menu of synthesizable delays, loops and couplings per unit of chip area, and graceful scaling as cells are added. There is a pleasing rhyme here — biology's honeycombs win on material per unit of enclosed area, and photonics' honeycombs win on circuits per unit of silicon. Hexagons, it seems, are simply good engineering, whoever the engineer is.
The FPGA analogy is irresistible and this course has leaned on it — but know exactly where it breaks. A LUT does not merely route its input; it regenerates it. Every stage of an FPGA snaps voltages back to clean digital rails, so a signal can traverse ten thousand LUTs and emerge perfect. The photonic mesh has no such mercy: it is a passive, analog fabric. Each real TBU costs ~0.3–0.5 dB of loss, so a twenty-TBU circuit loses a couple of dB and a thousand-TBU circuit would lose hundreds — there is no optical "level restorer" to call on, only amplifiers that add noise. Phase errors likewise accumulate rather than reset, which is why calibration is a control loop and not a one-off. The flip side of passivity is a genuine superpower the FPGA lacks: the fabric is transparent — it does not know or care what waveform passes through, so a single configuration carries 100 Gb/s data, analog RF and anything else inside its bandwidth untouched. Analog transparency and digital restoration are a trade, not a ranking — but never claim the mesh scales like the FPGA does. It does not, and loss is the reason.
A programmable fabric routes and filters whatever light you feed it — but feeding it remains the
expensive part: every wavelength channel wants its own laser. The