The parts bin is full: MZIs, phase shifters, rings, modulators, detectors, lasers. How does anyone
turn a folder of ideas into a diced, packaged, working photonic chip? The answer is a design flow
transplanted, organ by organ, from electronics — the same foundry model, the same GDSII masks, the
same shuttle runs that the
Four stations, one loop: when the tested chip disagrees with the simulation — and on a first spin it will, somewhere — the loop closes back to design, and the months start again. Everything in this lesson is about making each pass count.
As in electronics, you do not design for a process in general — you design for one foundry's process design kit. A photonic PDK contains the layer stack (silicon thickness, etch depths, doping implants, the Ge and heater modules), the design rules, and — its crown jewels — a component library: parameterised, silicon-validated building blocks. The foundry has fabricated and measured its grating couplers, splitters, phase shifters, ring filters and detectors across process corners, and publishes each as a black box with a layout cell and a measured S-parameter model (ports in, ports out, wavelength-dependent complex amplitudes — the same formalism as microwave engineering). The professional habit this teaches is humility: your design's novelty budget is finite, so spend it on the one custom device your idea actually needs and take everything else, gratefully, from the library. A circuit made of validated parts fails only in its new part — a circuit made of home-rolled couplers fails everywhere at once.
Simulation splits into two regimes that must not be confused. FDTD
(finite-difference time-domain) solves Maxwell's equations on a grid through one component — exact,
and exactly unaffordable at chip scale, since memory and time grow with volume over
That ten-line "simulation" — losses add in dB, margin is what's left — is genuinely how first-pass link budgets are done, and running out of margin on paper is a great deal cheaper than running out on silicon.
Layout produces the same artifact electronics ships: a GDSII file, polygons on numbered layers, one per mask step. But photonic geometry is a different dialect. Electronic layout is Manhattan — rectangles on a grid; photonic layout is curves — spirals, adiabatic tapers, S-bends, ring gaps — drawn as many-sided polygons on a nanometre grid, usually generated by Python frameworks rather than drawn by hand. Design-rule checking changes dialect too: alongside min-width and min-space, photonic DRC polices bend radii (too tight radiates light into the substrate), coupler gaps, and grid-snapping artifacts on curves. What it cannot police is function: photonics has only a weak analogue of electronics' LVS-and-extraction safety net, so "DRC clean" means manufacturable, not working.
Then the design goes to the fab — almost never alone. A full mask set costs from hundreds of thousands of dollars upward, so prototypes ride multi-project-wafer (MPW) shuttles: the foundry tiles dozens of customers' designs onto one reticle, everyone pays for their few square millimetres, and the shuttle departs on a published schedule a few times a year. A seat costs thousands rather than millions; the price is cadence — miss the tape-in date or botch the design, and the next boat is months away. Design reviews before a shuttle deadline have the atmosphere of a launch window.
Months later the wafers return, and the flow's most photonic-specific stage begins: test and packaging. Wafer-level testing works by pointing fibre probes at grating couplers — the one coupler type that fires vertically, so chips can be measured before dicing, thousands of structures overnight on an automated prober. Packaging is where photonics still hurts: a fibre must be glued to the chip edge holding sub-micron alignment through decades of thermal cycling, lasers must be attached or bonded, the electronics wire-bonded alongside — and this assembly, not the silicon, commonly dominates unit cost. Electronics solved its packaging with solder-ball self-alignment decades ago; photonics is still buying its way out one fibre at a time.
Rough current numbers, for calibration: a passive-silicon MPW seat of ~25 mm² runs on the order of €10–20k through brokers like Europractice or CMP on foundry platforms such as imec, AMF, AIM Photonics or GlobalFoundries; add active layers (junctions, Ge detectors, heaters) and the seat multiplies; a dedicated full-mask run starts in the high hundreds of thousands. The shuttle model is the same social technology that MOSIS pioneered for student CMOS chips in the 1980s — amortise the mask set across everyone on board — and it is quietly the reason university groups can afford to tape out photonic processors at all. The strategic consequence of "a few boats per year" is a design culture electronics has largely forgotten: you cannot iterate your way out of carelessness, so photonic groups over-instrument every tape-out — de-embedding structures, test rings, parameter sweeps of every gap and width — packing the margins of their seat with the experiments that will make the next seat's design right first time.
An electronics habit that must be surrendered at the border: treating layout as mere implementation
of a schematic that carries the real meaning. In a photonic chip the geometry is the
physics. A waveguide's width sets its effective index directly — a 1 nm width error shifts
This module built the parts and, now, the pipeline that turns parts into chips. Notice what the flow
lacks by electronics' standards — synthesis, abstraction layers, mature packaging, self-correcting
toolchains — because the shortfall is not a footnote: it is a standing tax on every photonic system
in the rest of this course, paid in tape-out months and calibration heaters. From here the course
stops building components and starts computing with them: Module 4 begins with the