Chip design is how text becomes silicon: hardware described in a language, proved correct, pushed through synthesis and place-and-route, and shipped as a die with billions of transistors. This master's-level course teaches the whole craft by building things — real SystemVerilog at every step — and aims it at the most remarkable chips of our era: it finishes with GPUs, from warp schedulers and rasterizers to tensor cores and chiplets, and a minimal working GPU you can watch execute a kernel cycle by cycle.
The arc: register-transfer-level design and industrial verification, FPGAs, the ASIC front-end
(synthesis, timing, clocks, power) and back-end (standard cells through tape-out, yield and
chiplets), then a RISC-V CPU built in RTL, a system-on-chip around it, and the GPU half — why
throughput processors exist, the compute microarchitecture, the graphics pipeline in silicon, the
modern frontiers, and the capstone build. It assumes fluency with
The subject's story runs through a remarkable cast: