The System Buses

A computer is not one lump of silicon — it is a small society of parts. The CPU does the thinking, main memory holds the program and its data, and a crowd of input/output (I/O) devices — the keyboard, the screen, the disk — feed things in and out. For any of this to be useful, these parts have to talk to each other. They do it over a set of shared wires called buses.

A bus is simply a bundle of parallel wires that carries information between components. Every device is tapped onto the same bundle, a bit like houses along a single street. In a von Neumann machine there are three cooperating buses, and each has one clear job:

the address bus — carries the address of the memory location (or I/O port) the CPU wants to use;
the data bus — carries the actual data (or instruction) being moved;
the control bus — carries control and timing signals that say what kind of operation this is and keep everyone in step.

This page teaches that trio: what each one does, which way the traffic flows, and — the exam favourite — why the width of a bus decides how much memory a computer can reach and how much data it can shift at once.

The three buses on one diagram

Step through the figure below. The CPU sits on the left; main memory and the I/O devices hang off the buses on the right. Watch the arrowheads carefully — they are the whole point. The address bus has a single arrowhead (traffic goes one way, out of the CPU); the data bus has arrowheads at both ends (traffic goes both ways).

Read a memory access as a little conversation. The CPU puts an address on the address bus ("I want box number 5"), raises a "read" signal on the control bus ("and I want to read it"), and memory answers by placing the contents of that box on the data bus, which travels back to the CPU. A write is the mirror image: the address goes out as before, but now the data flows from the CPU to memory, and the control bus carries a "write" signal instead.

Which way does the traffic flow?

The direction of each bus is not an arbitrary fact to memorise — it falls straight out of what the bus is for.

Address bus — one-directional (unidirectional). Only the CPU ever decides which location to access, so addresses only ever flow outward, from the CPU to memory and I/O. Memory never sends an address back; it just gets told which box to open. (In a machine with more than one bus master — say a DMA controller that can also drive memory — the address bus can be driven by more than one device, but for A-level treat it as CPU → memory.)
Data bus — bidirectional. On a read the data flows memory → CPU; on a write it flows CPU → memory. Since the CPU does both, the wires must carry data in both directions (never both at the same instant — the control bus says which way this time).
Control bus — bidirectional. Some signals go out from the CPU (read/write, address-valid, clock), and some come back in to it (interrupt requests, "I'm not ready — wait" signals from slow devices). So overall the control bus carries signals in both directions too.

The address bus width sets how much memory you can reach

Here is the idea the exam boards love. Each wire in the address bus carries one binary digit — a 0 or a 1 — so an address bus with n wires can send out an n-bit address. And an n-bit number has exactly 2^n possible patterns, from all-zeros to all-ones. Each distinct pattern names one memory location, so:

An address bus of width n can address 2^n \text{ distinct locations.}
Add one wire and you double the number of locations you can reach.
Widening the address bus lets a machine reach more memory — it does not make memory faster.

Because each address usually names one byte, the count of locations is also (roughly) the maximum memory in bytes. Work through the pattern — notice how fast 2^n grows:

n = 8 wires \to 2^8 = 256 locations.
n = 16 wires \to 2^{16} = 65{,}536 locations (that's 64 KiB — exactly the limit of many 1980s home computers).
n = 20 wires \to 2^{20} = 1{,}048{,}576 locations (1 MiB — the original IBM PC).
n = 32 wires \to 2^{32} \approx 4.3 billion locations (4 GiB — why 32-bit machines cap out around 4 GB of RAM).
n = 64 wires \to 2^{64} — about 1.8 \times 10^{19} locations, so much that no machine comes close to filling it.

You can watch the doubling happen. Drag the slider to change the number of address wires and read off how many locations that reaches:

The data bus width sets how much moves per trip

The data bus obeys the same "more wires = more at once" logic, but for a different quantity. Its width is how many bits travel together in a single transfer. A machine with an 8-bit data bus moves one byte per trip; a 64-bit data bus moves eight bytes per trip.

So a wider data bus doesn't let you reach more memory — it lets you shift more data per transfer, which (all else equal) means more work done per clock tick. This is a big part of what "a 64-bit processor" means in everyday speech: wider registers, a wider data path, and the ability to move 64 bits in one go.

A tiny program makes the address-bus rule concrete — it just computes 2^n for a few bus widths:

function addressableLocations(addressWires: number): number { return 2 ** addressWires; // 2^n distinct addresses } for (const n of [8, 16, 20, 32]) { console.log(`${n} address wires -> ${addressableLocations(n).toLocaleString()} locations`); }

Watch out

Two mistakes cost easy marks in this topic. Get them straight now.

1. The address bus is one-directional; the data bus is bidirectional. Addresses only ever leave the CPU (CPU → memory) — memory never sends an address back, it just receives the one it's told to open. Data, on the other hand, has to travel both ways, because the CPU both reads data out of memory and writes data into it. If an exam answer says "the data bus is one-way" or "the address bus is two-way", it's wrong.

2. A wider address bus means more addressable memory (2^n), not a faster computer. Adding an address wire doubles how many locations you can name — it says nothing about how quickly data moves. Speed is influenced by other things (the clock, the data-bus width, cache). Mixing up "more memory" with "more speed" is the single most common slip here.

A neat corollary of trap 2: going from n to n+1 address wires doubles the reach, so the jump from a 16-bit to a 32-bit address bus is a factor of 2^{16} = 65{,}536 — not a factor of 2.

The 1981 IBM PC used an Intel 8088 with a 20-wire address bus, so it could address 2^{20} = 1 MiB of memory. But IBM reserved the top chunk of that space for the screen, the BIOS and expansion cards, leaving only the bottom 640 KB for programs. That "640K ought to be enough for anybody" limit haunted PC software for a decade — a perfect reminder that the address bus sets the ceiling, but the system designers decide how the space underneath it is carved up.

Worked example

A processor has a 24-bit address bus and a 16-bit data bus. (a) How many memory locations can it address? (b) How many bytes move in one data-bus transfer?

(a) Addressable locations = 2^{24} = 16{,}777{,}216 — that's 16 MiB if each location is one byte.
(b) A 16-bit data bus carries 16 bits = 2 bytes per transfer.

Notice the two answers come from different buses and answer different questions — "how much can I reach?" versus "how much moves at once?". Keeping those apart is most of the skill.