The MOSFET as a Switch

Descend far enough down the abstraction stack and every adder, cache and CPU dissolves into one humble component repeated a few billion times: the MOSFET — the Metal-Oxide-Semiconductor Field-Effect Transistor. A modern Apple or AMD chip packs on the order of 10^{10} of them. To an architect the miracle is not the device physics but the abstraction it offers: a MOSFET behaves like a tiny voltage-controlled switch. Put the right voltage on one terminal and a connection between the other two snaps closed; remove it and the connection opens. Everything digital is built out of that one trick.

You already know how a semiconductor conducts. Here we bottle that behaviour into a switch you can command, and meet the single most important detail: there are two flavours of switch, and each is only good at passing one of the two logic values cleanly. That asymmetry is the reason CMOS logic comes in complementary pairs.

Three terminals and a command

A MOSFET has three terminals that matter for logic (a fourth, the body or bulk, is normally tied to a supply rail and we will quietly ignore it):

the gate (G) — the control input; the voltage here decides whether the switch is open or closed;
the source (S) and drain (D) — the two ends of the switched connection, the channel that either conducts or does not.

The gate sits over a thin insulating layer of oxide — it is one plate of a capacitor, not a wire into the channel. That is why the gate draws essentially no steady current: you are charging a capacitor, not pushing current through a resistor. This is the property that lets logic gates fan out to many inputs almost for free, and it is why static CMOS burns almost no power while it sits still.

NMOS: closes when the gate goes HIGH

An NMOS transistor conducts when its gate is pulled to a high voltage relative to its source. Precisely, it turns on once the gate-to-source voltage climbs past a positive threshold voltage V_{th} (a device constant, typically a few tenths of a volt):

\text{NMOS is ON} \iff V_{GS} > V_{th}, \qquad V_{th} > 0.

Below threshold the channel is empty and the switch is open; above it, a conducting layer of electrons forms and source and drain are joined. Think of it as a switch whose control logic is "close me when the gate is 1."

PMOS: the mirror image — closes when the gate goes LOW

A PMOS transistor is the complement. Its threshold is negative, and it conducts when the gate is pulled below the source by more than |V_{th}|:

\text{PMOS is ON} \iff V_{GS} < V_{th}, \qquad V_{th} < 0.

In a logic circuit the PMOS source sits at the top rail V_{DD}, so "gate low" means a logic 0 on the gate turns it on. NMOS closes on a 1; PMOS closes on a 0. They are controlled by opposite commands — hence complementary MOS, CMOS.

an NMOS is ON when V_{GS} > V_{th} (gate high) and OFF when the gate is low;
a PMOS is ON when V_{GS} < V_{th} (gate low) and OFF when the gate is high;
the gate commands the switch and draws ~no DC current (it is a capacitor plate); the switched path runs between source and drain.

The crucial asymmetry: strong and weak values

Here is the fact that shapes all of CMOS. Each switch passes one logic value cleanly and the other value degraded. An NMOS is superb at pulling a node down to ground — it passes a strong 0. But when you try to pass a high voltage through an NMOS, it stops conducting as the output approaches V_{DD} - V_{th}: the moment V_{GS} falls back below V_{th} the channel closes. The result is a weak 1, short of the full rail by a threshold drop.

PMOS is the mirror image: brilliant at delivering the full V_{DD} — a strong 1 — but it can only drag a node down to |V_{th}| above ground, giving a weak 0. So the design rule writes itself: use NMOS to pull down to 0, use PMOS to pull up to 1, and never ask either to do the other's job.

Device	Turns ON when gate is…	Passes cleanly	Passes badly
NMOS	HIGH (V_{GS} > V_{th})	a strong 0 (down to GND)	a weak 1 (stops at V_{DD}-V_{th})
PMOS	LOW (V_{GS} < V_{th})	a strong 1 (up to V_{DD})	a weak 0 (stops at \|V_{th}\|)

Model it in code

The switch abstraction is so clean you can capture both devices in a few lines. We model a rail as a voltage and ask each transistor whether it conducts, and what quality of value it would deliver.

// A minimal switch-level model of NMOS and PMOS transistors. const VDD = 1.0; // supply rail (volts), a logic 1 const VTH = 0.3; // threshold magnitude // Is the device conducting, given gate and source voltages? function nmosOn(vGate: number, vSource: number): boolean { return (vGate - vSource) > VTH; // needs Vgs > +Vth } function pmosOn(vGate: number, vSource: number): boolean { return (vGate - vSource) < -VTH; // needs Vgs < -Vth } // NMOS driven from ground passes a strong 0; try to pass VDD and it self-limits. console.log("NMOS, gate=1, pulling a node toward GND:"); console.log(" conducts? " + nmosOn(VDD, 0)); // gate high, source at 0 -> ON console.log(" best HIGH it can output ~ " + (VDD - VTH).toFixed(2) + " V (a WEAK 1)"); console.log("PMOS, gate=0, pulling a node toward VDD:"); console.log(" conducts? " + pmosOn(0, VDD)); // gate low vs source at VDD -> ON console.log(" best LOW it can output ~ " + VTH.toFixed(2) + " V (a WEAK 0)");

The thin oxide under the gate is what makes the transistor a field-effect device: the gate controls the channel by its electric field, not by injecting current. That insulation is worth a fortune. Because no DC flows into the gate, a logic output can drive dozens of downstream gates without its voltage sagging, and an idle circuit dissipates almost nothing. The price is that the gate is a capacitor you must charge and discharge every time it switches — and charging capacitors through resistive wires is exactly the delay and the dynamic power that dominate everything from here on. The insulator that saves static power sets the switching speed. That oxide is now only a handful of atoms thick, which is one of the hard walls of modern scaling.

A tempting mistake: "the NMOS gate is a 1, so its output is a 1." No. The gate value says whether the switch is closed, not what value comes out. A closed NMOS connects its drain to whatever its source is wired to — in logic that source is ground, so a closed NMOS drives the output toward 0. NMOS switches on with a gate 1 but outputs a 0. This inversion is not a nuisance; it is the reason the natural CMOS gate is the inverting NAND, and why a plain AND costs an extra transistor pair.

Why this abstraction is the whole game

Once you accept "voltage-controlled switch," the rest of digital design is combinatorics on switches: wire switches in series to demand that all their gates agree, in parallel to accept any of them, and you have built AND-like and OR-like conditions out of physics. The next lesson does exactly that, pairing NMOS pull-down networks with PMOS pull-up networks to build gates that always drive a strong value and burn no static power. Every flip-flop, adder and multiplier you meet later is a large, cleverly arranged crowd of these two little switches.