Technology Scaling and the Interconnect Wall

For forty glorious years, the recipe for a faster computer was almost embarrassingly simple: make the transistors smaller. Every couple of years a new process node — 90 nm, then 45, 22, 7, 5, 3 — packed twice as many transistors into the same area, and each one switched faster and used less power. That is Moore's law working hand in hand with Dennard scaling, and it carried the industry from megahertz to gigahertz almost for free. But somewhere around the mid-2000s the free lunch ran out — and one of the villains, the one this lesson is about, is deceptively humble: the wires. Transistors kept getting faster; the wires connecting them refused to. That is the interconnect wall.

What "a node" actually buys you

The feature size (or node) is a rough label for the smallest structures a fabrication process can print. Shrinking it by a factor k (classically k \approx 0.7 per node, so area halves) historically delivered a triple win:

more transistors — density scales as 1/k^2, so you get twice as many per unit area;
faster gates — a smaller transistor has less capacitance to charge, so its switching (gate) delay shrinks with the feature size;
lower power per transistor — Dennard scaling let voltage drop alongside size, keeping power density roughly constant.

Two of those three still largely hold — you still get more, denser transistors, and their gate delay still falls. It is the interaction with wires and with power that broke, and it changed the whole game.

Why wires don't scale: the RC problem

A wire is not free. It has resistance R and capacitance C, and a signal takes time \sim RC to charge it up. Now shrink everything. A wire's resistance is R = \rho \dfrac{L}{A}: make it thinner (smaller cross-section A) and R goes up. Its capacitance to ever-closer neighbours does not fall. So while a gate got faster as it shrank, a wire of a given length got no better, and often worse. Worse still, delay along an unbuffered wire grows with the square of its length:

t_{\text{wire}} \;\sim\; R\,C \;\propto\; \Big(\tfrac{L}{A}\Big)\big(L\big) \;\propto\; L^2.

Local wires (a few gates apart) shrink along with the logic and stay quick. But global wires — the ones that must cross the whole chip to reach a distant cache or unit — do not get shorter as the chip stays the same size, so their delay stubbornly refuses to fall. As gate delay keeps dropping, a growing share of every cycle is spent not computing but simply waiting for a signal to travel down a wire.

The crossover: watch the walls trade places

Plot gate delay and (global) wire delay against the technology generation. Gate delay slides down node by node; wire delay sits flat or creeps up. Somewhere they cross — and past that node, the wire, not the gate, is the slow part of the path. Drag the wire-length slider: longer global wires cross the gate-delay curve at an earlier node, which is exactly why keeping data physically close became a first-class design goal.

shrinking the feature size gives more, denser transistors whose gate delay falls — Moore's law and (formerly) Dennard scaling;
wire (RC) delay does not scale: thinner wires raise resistance, and unbuffered delay grows as L^2, so global wires stay slow;
past a crossover node, interconnect delay dominates the critical path — "smaller" stopped automatically meaning "faster."

How designers fight the wire

Engineers did not take this lying down. The counter-attacks are worth knowing:

Problem	Fix
Delay grows as L^2 on long wires	Repeaters: insert buffers along the wire to break it into segments, turning L^2 into roughly linear L
Aluminium wires too resistive	Switch to copper interconnect (~2000) — lower \rho
Capacitance between packed wires	Low-\kappa dielectrics between wires to cut C
Global wires just too long	Architecture: keep data local — caches, tiling, networks-on-chip, and many small cores instead of one big one

That last row is the deepest. When a signal cannot cross the chip in a cycle, you stop trying to build one enormous fast core and instead build many cores that mostly talk to their own nearby memory. The interconnect wall is one of the quiet reasons the industry pivoted to multicore.

See the crossover in numbers

Let gate delay fall ~30% per node while a fixed-length global wire's delay holds roughly steady (even creeping up). Watch which term wins as the nodes advance.

// Gate delay shrinks each node; a fixed-length global wire's delay does not. function gateDelayPs(gen: number): number { return 20 * Math.pow(0.7, gen); // ~30% smaller per node } function wireDelayPs(gen: number, lenRel: number): number { return lenRel * lenRel * (5 + 1.0 * gen); // ~L^2, flat-to-rising per node } const L = 1.5; // relative length of a global wire console.log("gen | gate(ps) | wire(ps) | slower part"); for (let g = 0; g <= 7; g++) { const gate = gateDelayPs(g), wire = wireDelayPs(g, L); const dom = wire > gate ? "WIRE" : "gate"; console.log(`${g} | ${gate.toFixed(1).padStart(5)} | ${wire.toFixed(1).padStart(5)} | ${dom}`); } console.log("Early nodes: the gate is slower. After the crossover: the WIRE dominates.");

Because the wire problem is fundamentally about distance, and a flat chip forces long horizontal journeys. 3D integration — stacking dies and joining them with dense vertical connections (through-silicon vias), and putting memory right on top of logic (HBM, hybrid bonding) — shortens the longest wires by folding the chip into the third dimension. A signal that had to cross millimetres of silicon now travels micrometres straight up. This is why HBM stacks sit millimetres from GPU compute, and why "chiplets" glued on a fast interposer (AMD's approach) beat one giant monolithic die: keeping communicating things physically close is now a primary architectural lever, not an afterthought.

The old reflex — new node, therefore faster — is now wrong, and marketing muddies it further (node names like "3 nm" no longer correspond to any physical dimension; they are just labels). A shrink still gives you more transistors and quicker gates, but if your critical path is dominated by global wire delay, moving to a smaller node barely helps that path — the wire didn't shrink. Real speedups now come from architecture: shorter wires, more locality, parallelism, specialisation. Never assume a die shrink alone buys frequency; check whether gates or wires sit on your critical path first.

The end of a simple era

This is where the "just shrink it" chapter of computing closes. Transistors are still improving, but the wires between them, the power they dissipate, and the atoms they are running out of have turned raw scaling from a guarantee into a grind. The consequence shapes everything above it in the stack: because you can no longer buy speed by making one core faster, you buy it by making many cores, specialised accelerators, and memory hierarchies that fight to keep data close. The physics we descended into over this module is exactly what pushes the rest of computer architecture back up toward parallelism and locality.