STA hands you a report full of negative slack. Now what? Timing closure is the negotiation that follows — between you, the tools, and physics — until every path's slack is non-negative at the target clock. It is where chip design stops feeling like programming and starts feeling like diplomacy: you state your terms, the tool counters with what silicon can actually do, and you both make concessions until the report reads all zeros and pluses. Whole tape-out schedules live or die on how this negotiation goes.

Constraints: the contract

The negotiation starts from a written contract — the constraints file (SDC). Its clauses:

• create_clock — the clock's period and source: the headline demand ("1.25 ns, please").
• input/output delays — how much of the period is already spent outside this block, so boundary paths are budgeted honestly.
• false paths — paths that exist in the gates but never in the function: between two mutually-exclusive modes, from a configuration register written once at boot, across a handshake that guarantees stability. Declaring one tells STA "do not check this"; the path vanishes from the report and stops throttling optimisation.
• multicycle paths — data legitimately allowed N \ge 2 cycles to cross, because the receiving logic samples only every Nth edge. The check relaxes to N \cdot T_{\text{clk}}.

Exceptions are power tools: each one deletes checks. Wielded correctly they recover real performance that pessimism was wasting; wielded sloppily they hide real failures — see the Watch out below.

The fix toolbox, in escalating order

A path misses timing. The remedies come in a natural escalation — cheapest and most automatic first:

• Let the tools try harder. Upsize drive strength (swap a cell for its beefier sibling — faster, at some area and power); buffer long wires; restructure logic (rebalance a lopsided gate tree, factor differently, duplicate a gate to split its load). Synthesis and the physical tools do all of this automatically when pushed.
• Pipeline the path. Add a register in the middle — the RTL move you already know from the sequential-logic lessons: throughput is kept (one result per cycle), latency grows by one cycle, and each half only has to fit half the logic in a period. This changes cycle-level behaviour, so it is a designer decision, not a tool's.
• Retime. Slide existing registers through logic — moving a register from a gate's output to all of its inputs (or vice versa) preserves the function while rebalancing the stage delays. Tools do this legally and automatically when allowed; unlike pipelining it adds no latency.
• Restructure the algorithm. When no amount of pushing gates helps, change the maths: a ripple-carry adder's delay grows linearly in width, a carry-select or parallel-prefix adder's logarithmically. The biggest timing wins in history are algorithm swaps, not gate tweaks.
• Floorplan hints. Sometimes the delay is wire: two talkative blocks placed far apart. Telling the back-end to keep them adjacent shortens the path without touching a single gate.

Hold violations get the opposite medicine — adding small delay cells to too-fast paths — and that fixing is usually left to the back-end flow, after placement, when the real wire delays are known.

The flagship move, drawn

Here is pipelining as the timing tools see it — a chain of four logic blocks (0.9, 0.8, 1.1 and 0.7 ns) between two registers, with 0.15 ns of register overhead (t_{cq} + t_{\text{setup}}) per stage:

Note where the cut went: after the second block, the most balanced split available. Cut after the first block instead and the second stage would carry 2.6 ns — the clock is always set by the worst stage, so an unbalanced cut wastes the register you spent. The little program below tries every cut:

The closure loop — and its diminishing returns

Closure is iterative: synthesize → run STA → fix the worst paths → repeat. The first loop kills the outliers cheaply (a few upsized cells); each following loop digs into a broader, harder layer of paths. Progress follows a wall-of-slack curve: the worst negative slack improves quickly, then crawls, because fixing one path promotes the runner-up to critical — whack-a-mole with thousand-path moles. Experienced teams watch not just WNS (worst negative slack) but TNS (total negative slack, the sum over all failing endpoints): WNS tells you how far physics is from the contract, TNS tells you how much of the design is fighting you. When hundreds of endpoints fail by a lot, no cell upsizing will save you — that is the signal to reach for the deeper tools: pipeline, retime, or change the algorithm.