Your design now meets timing. The next bill arrives: power. You met the power wall as an architectural fact; front-end design is where you actually fight it, cycle by cycle and net by net. Dynamic power obeys one formula worth tattooing somewhere:

where f is the clock frequency, V the supply voltage, C the capacitance being switched, and \alpha the activity factor — the fraction of cycles a given net actually toggles. Every charge-up of a net costs \tfrac{1}{2}CV^2 from the supply, dumped as heat on the way back down (the deeper physics of that half-CV² — and the strange far horizon where computing needn't dissipate at all — lives in the energy cost of switching). The front-end levers are \alpha and C; the next lesson pulls the mighty V and f levers. And one net towers over all others in \alpha…

The clock: the hungriest net on the chip

Data nets toggle when data changes — \alpha is typically 0.05–0.2. The clock toggles every single cycle, by definition: \alpha = 1, the maximum possible, into an enormous capacitance — the buffer tree spanning the die plus the clock pin of every flip-flop. Multiply the biggest \alpha by one of the biggest Cs and you get the standard, slightly scandalous fact: the clock network burns 30–50% of many chips' dynamic power — much of it delivered to registers that are not even changing value. A register holding the same word for a thousand cycles still receives, and pays for, a thousand clock edges.

Hence the biggest single power optimisation in digital design: clock gating — switch the clock off for registers with nothing to do. Slide the sliders: the savings scale with how much of the clock tree you can gate and how often those registers are genuinely idle.

Gating the clock without wrecking it

The obvious circuit is a trap. Write assign gclk = clk & en; and whenever en changes while the clock is high, the AND output changes mid-cycle — emitting a partial-width runt pulse or truncating a real one. Downstream flip-flops may treat the runt as a genuine clock edge and capture garbage — occasionally, unreproducibly, on every flop downstream of the gate. The industrial fix is the integrated clock-gating cell (ICG): a level-sensitive latch, transparent while the clock is low, feeding the AND. The latch freezes the enable for the entire high phase, so the gated clock can only ever produce full, clean pulses:

You almost never instantiate an ICG by hand. Write enable-based RTL and the tools infer it:

A register bank written this way tells synthesis exactly which cycles matter; the tool replaces the per-bit feedback muxes with one ICG driving the bank's clock pin — hundreds of clock pins silenced by one gate. This is the pleasing pattern of low-power design: say what you mean in RTL, and let the tool turn intent into savings.

Beyond the clock: making the data hold still

Once the clock is gated, the remaining dynamic power is data toggling — shrink \alpha and C there too:

• Operand isolation — a big combinational block (a multiplier, say) whose result is only used sometimes still ripples with every input twitch, burning power computing answers nobody reads. Freeze its inputs (an AND mask or an enabled register) when the result is unused, and the whole cloud goes quiet.
• Encoding choices — a one-hot state machine toggles exactly two bits per transition; a dense binary encoding can toggle many at once (7 → 8 flips four). Buses that count or step can use Gray code for the same reason it helped in the CDC lesson: fewer transitions, less \alpha.
• Avoid wasteful recomputation — hoist the invariant work out of the every-cycle path, exactly as you would hoist code out of a loop: compute once, register it, reuse it.

And measure, don't guess: power tools re-run the netlist against switching-activity data recorded from realistic simulations, producing a report of exactly which nets and clocks burn what. Here is that style of accounting in miniature: