The LUT fabric can be anything — that is its glory and its curse. Try to build a 64-kilobit buffer out of LUTs and you will burn tens of thousands of them on a structure that a memory designer could lay out in a speck of dense SRAM. Try to build one 18×18 multiplier and hundreds of LUTs vanish into partial products, running at half the speed a custom multiplier would manage. Universality has a price, and for the handful of structures every design needs — memories, multipliers, clock circuits — the price is absurd. So FPGA architects made a deal: sprinkle the fabric with small islands of hardened, fixed-function silicon for exactly those structures. This lesson is about those islands, and about the quiet art of writing RTL so the tools actually use them.

The islands in the sea

• Block RAM (BRAM). Columns of dense SRAM blocks — classically 36 kilobits each — threaded through the fabric. Each block is dual-ported (two independent ports can read or write in the same cycle, perfect for a FIFO with a writer on one side and a reader on the other) and reshapeable: one 36 Kb block can present itself as 1K × 36, 2K × 18, 4K × 9, and so on. A big buffer stitches several blocks together.
• Distributed LUT-RAM. The other memory option: a LUT's 64-bit table is itself a tiny RAM, and some slices let you write it at runtime. Below roughly a few hundred bits — register files, small FIFOs — LUT-RAM sits right next to the logic that uses it and wastes no 36 Kb block; above that, BRAM wins overwhelmingly. Knowing where the crossover lies is part of the craft.
• DSP slices. Hardened multiply-accumulate datapaths (the classic is Xilinx's DSP48: an 18×18 → 36-bit multiplier feeding a 48-bit accumulator, with optional pre-adder and pipeline registers). One slice does at full clock rate what ~300 LUTs do slowly. A signal-processing or machine-learning design lives and dies by its DSP count.
• Clock managers (PLLs/MMCMs). Analogue-flavoured circuits that multiply, divide and phase-align clocks — you cannot synthesise a PLL from LUTs at all.
• SerDes transceivers. Serialiser/deserialiser pairs driving multi-gigabit serial links (PCIe, Ethernet, displays). Again physically impossible in fabric: this is high-speed analogue design, hardened at the die edge.
• Hard processor systems. The biggest island of all — entire ARM clusters baked in beside the fabric — big enough to get its own lesson next.

Where the islands sit

The floorplan makes the deal visible: a vast regular sea of CLBs, interrupted by skinny columns of BRAM and DSP (columns, so the regular routing pattern survives), with the exotic analogue blocks pushed to the edges:

Inference: writing RTL the tools recognise

How do you use a DSP slice or a BRAM? Mostly, you don't ask — you describe a pattern the synthesis tool recognises, and it maps your RTL onto the hard block for you. This is called inference, and it keeps your RTL portable across vendors. The two patterns that matter most:

The alternative is explicit instantiation: placing the vendor's primitive (DSP48E2, RAMB36E2…) in your netlist by name, port by port. You get exact control and zero portability; teams reserve it for the cases where inference cannot express what the block can do. The professional default is: infer, check the report, instantiate only when forced.

"Check the report" is the load-bearing phrase. Every FPGA build prints a utilization report — a table of how much of each resource the design consumed:

Read it like a doctor reads bloodwork. This design is LUT-light but has all-but-exhausted its DSPs — one more multiplier and the tools start building multipliers from LUTs, and speed falls off a cliff. A surprise in the report is also your best bug detector: if you meant to infer one BRAM and the report shows zero BRAMs and five thousand extra LUTs, the tool did not recognise your pattern — which brings us to the classic way that happens (see the Watch out below).

Counting the cost: DSPs versus LUT multipliers

Make the economics concrete. Suppose a matrix-multiply engine needs P parallel multiply-accumulate units, on a mid-range part with 274 000 LUTs and 2 520 DSP slices. Each MAC is either one DSP slice or roughly 300 LUTs:

The fabric version hits the wall around 900 MACs while the DSP version sails to 2 520 — and every one of those LUT-built MACs would clock slower besides. Same die, wildly different capability, purely because someone hardened the right islands.