The Chip Industry Landscape

You have designed an ISA, written the RTL, dispatched the blocks, survived the memory system, watched a kernel run end to end, and audited the road from toy to titan. One lesson remains, and it contains no new circuits at all. It answers the question every capstone earns: where does all this live in the world — and where could you live in it? The chip industry is not one industry but an interlocking system of four estates — those who make, those who design, those who build the tools, and those who sell designs themselves — plus a rising open-source commons where a student really can get real silicon back in the mail. This is the map.

The four estates

Foundries — TSMC, Samsung Foundry, Intel Foundry — own the fabs where wafers are actually printed and sell process nodes as products: a node is a manufacturing recipe plus design rules plus transistor models, versioned and priced like software platforms. The entry fee explains the census: a leading-edge fab costs on the order of $20 billion, so only about three players on Earth can still make leading-edge logic — and one of them makes most of it;
Fabless designers — NVIDIA, AMD, Apple, Qualcomm — do everything this course taught except manufacturing. They carry the architecture, RTL, verification and physical design, then buy wafer capacity from a foundry. The fabless model, barely four decades old, is why a company can field a world-beating chip without ever owning a cleanroom;
EDA vendors — Synopsys, Cadence, Siemens EDA — build the software this course kept invoking: simulators, synthesis, place-and-route, timing signoff, DRC. Three companies, a few tens of billions in combined revenue, sitting underneath a trillion-dollar electronics economy — the highest leverage-per-employee corner of the whole map;
IP vendors — Arm above all — sell designs as products: pre-built, pre-verified module subtrees (CPU cores, interconnects, memory controllers, PHYs) that fabless teams license instead of reinventing. When you instantiated a module and trusted its interface, you were rehearsing the IP economy in miniature.

A single phone chip threads through all four: licensed Arm cores and interface IP, assembled and extended by a fabless design team, using EDA tools end to end, printed by a foundry — four estates, one die.

The open commons — and your own tapeout

For fifty years the flow you learned was locked behind commercial licences and NDAs. That wall is now visibly cracking: RISC-V is an open ISA with an ecosystem of open cores; Yosys and OpenROAD are open-source synthesis and place-and-route good enough to produce manufacturable GDSII; open PDKs describe real foundry processes; and shuttle programmes — pioneered by efabless and carried on by community successors — aggregate many small designs onto one shared wafer run. The consequence is genuinely new: a student can tape out. Not "simulate", not "run on an FPGA" — receive packaged, functioning custom silicon of their own design. The Tiny Tapeout vignette below has the concrete path. Open silicon is today roughly where open-source software was in the late 1990s: not yet how the flagship products ship, but unmistakably where the curious are learning — and history suggests you should never bet against where the curious are learning.

One honest paragraph of geopolitics, because the industry cannot be understood without it. Leading-edge manufacturing is concentrated to a degree unmatched by any other strategic technology — most of it on the island of Taiwan — and fabs cannot be duplicated quickly at any price: a new one takes years, $20 billion, and an ecosystem of suppliers that itself took decades. Governments have responded with export controls on advanced chips and tools, and with subsidy programmes (the US and European CHIPS Acts among others) to pull fabs back onshore. Whatever your politics, the professional takeaway is plain: chip-making is now treated by every major power as critical infrastructure, which means the skills this course teaches sit permanently on the strategic agenda — with all the funding, scrutiny and job security that implies.

Careers: the course as a map of the professions

Each estate hires the modules you just studied. The table is the honest version of "what would I actually do all day?":

Role	This course's modules	Daily tools	Who hires
RTL / digital design	RTL (M1) · CPU (M6) · SoC (M7)	SystemVerilog, lint, synthesis reports	fabless, IP vendors
Verification	Verification (M2)	UVM testbenches, simulators, formal tools, coverage	everyone — the most-hiring discipline in the industry, typically ~2 verification engineers per designer
Physical design	Front-end → GDSII (M4) · Back-end (M5)	place-and-route, static timing, DRC/LVS signoff	fabless, foundries, EDA
Architecture / performance	Parallelism (M8) · GPU compute (M9) · Graphics (M10) · Frontiers (M11)	performance simulators, profilers, workload analysis	fabless, hyperscalers
EDA / tool development	all of them, plus serious software engineering	C++, algorithms, the flow itself as the product	EDA vendors, open-source projects
GPU teams	every module at once — this capstone in the large	all of the above	NVIDIA, AMD, Apple, Intel, and a wave of startups

And the closing chord. This course opened with a promise that reads differently now than it did then: text becomes silicon. You have since watched the sentence execute — your assembly became words, your RTL became a machine, your machine ran your kernel and proved itself right. The industry mapped on this page is that same sentence executed at planetary scale: hundreds of thousands of people, four estates, a supply chain spanning every continent, all of it a machine for turning carefully-written text into working matter. It is one of the great collective engineering projects of our species, it is nowhere near finished — and there is room in it for you.

Here is the concrete, no-asterisks path to your own chip. Tiny Tapeout sells tiles on a communal die: you design a small circuit — Verilog, or even a drawn logic diagram — against a simple standard interface, submit it through an automated open-source flow (Yosys and OpenROAD under the hood), and your design is printed alongside a few hundred others on a shared shuttle run at a real foundry. Cost: on the order of a hundred-ish dollars for a tile — textbook money, not fab money — and some months later a demo board arrives with the die on it, a multiplexer letting you select your project among its neighbours. Students have shipped counters, tiny CPUs, synthesizers, pong. A four-lane PrimerGPU core would need some dieting to fit a tile — but a lane, an ALU, or the dispatcher's arbiter fits with room to spare. There has never before been a moment when the full sentence of this course — text in, silicon back — was executable by one curious person with pocket money. It is now.

You will hear it: "everything is software now — hardware is a shrinking backwater". Look at the actual market instead. AI has made compute the scarce resource of the decade; every hyperscaler is designing custom silicon; governments are subsidising fabs on three continents — and the universities stopped producing enough chip engineers years ago. The shortage is real, global, and worst precisely at the seam this course occupies: people who understand hardware and write serious code — who can build a simulator, script a flow, debug RTL with a software engineer's tooling instincts. That is not a compromise profile; it is the profile every GPU team, EDA vendor and architecture group is bidding for, and the scarcity premium shows in the offers. If you enjoyed building PrimerGPU — the code and the hardware thinking — you did not just pass a course; you sampled the most under-supplied job description in computing.