Eleven modules ago this course promised that text becomes silicon. The capstone collects on that promise: over the next five lessons we will design and simulate a complete, working GPU — PrimerGPU — with SIMT cores, a block dispatcher and an honest, bottlenecked memory system. And every machine ever built starts in the same place: not with gates, but with a contract. Before a single flip-flop exists, someone writes down exactly what software may ask the hardware to do — the instruction set architecture. We did this once before, when we planned a CPU around an RV32I subset; now we do it again for a machine whose whole reason to exist is running one program as ten thousand threads. After touring real GPUs all the way out to chiplet monsters, it is time to build our own — small enough to fit in your head, real enough to breathe.

Design goals: minimal, but sufficient

A good tiny ISA is ruthless about what it leaves out. Our contract has three clauses:

• Sufficient — it must express real data-parallel kernels: vector addition and matrix multiplication, the two workloads that justify a GPU's existence. That forces arithmetic, loads, stores, an immediate, a compare, and a conditional branch (matmul's inner loop needs one).
• Minimal — nothing that isn't forced. Eleven instructions, 16-bit fixed-width encodings, one flat data memory. No floats, no stacks, no interrupts, no modes.
• SIMT-native — the thread's identity is part of the architecture. Three registers are hard-wired to tell each thread who it is. This clause is the one that makes it a GPU ISA rather than a small CPU ISA, and it deserves its own section below.

Every choice from here on — 4-bit register fields, 8-bit immediates, a single condition-flag set — follows from squeezing those clauses into sixteen bits.

The PrimerGPU ISA: eleven instructions

Each instruction is one 16-bit word: a 4-bit opcode in bits 15–12, then register or immediate fields. Rd is the destination (bits 11–8), Rs and Rt are sources (bits 7–4 and 3–0), imm8 is an 8-bit unsigned immediate (bits 7–0):

Two entries repay a second look. BRnzp is a predicated branch borrowed in spirit from the LC-3: CMP compares two registers and records whether the result was Negative, Zero or Positive; the branch carries a 3-bit mask saying which of those outcomes it fires on. BRnzp n, #4 branches to address 4 if the last compare came out negative — a loop condition in two instructions. And RET is not "return a value"; it is a thread announcing my work here is done — the signal the machinery of the next three lessons will collect, count, and turn into "kernel complete".

Reading a word

Sixteen bits, four fields, no exceptions to memorise — here is instruction 9 of the kernel we are about to write, taken apart:

Fixed fields are a gift to the decoder: bits 11–8 are always where a destination would live, bits 7–4 always the first source. In the next lesson the decode logic will be a page of combinational SystemVerilog precisely because we kept this table boring.

Sixteen registers — and the three that make it a GPU

Every thread owns sixteen 16-bit registers. Thirteen are ordinary scratch space. The last three are the whole trick:

This is the SIMT index magic — as architecture. Every thread runs the same instruction words, but each thread's R13–R15 are wired to its own coordinates by the hardware. The one expression every kernel opens with,

therefore evaluates to a different number in every thread: thread 2 of block 1 with 4-thread blocks gets i = 1 \times 4 + 2 = 6, its neighbour gets 7. One program text, ten thousand different executions — the entire SIMT idea, delivered by three read-only registers. Addressing follows for free: with arrays laid out flat in one data memory (say a at 0, b at 8, c at 16 for 8-element vectors), thread i touches a[i] at address 0+i, b[i] at 8+i — plain register arithmetic, no special addressing modes needed.

The first kernel: vector add, line by line

Here is c[i] = a[i] + b[i] over 8 elements, as every thread of every block will run it — 13 words, no loops, because the parallelism is the loop:

Walk it as thread 3 of block 1 (blocks of 4): lines 1–2 compute i = 1\times4+3 = 7; lines 3–5 pin down the memory layout; lines 6–9 fetch a[7] and b[7] (note the idiom LDR R4, R4 — the address goes in, the data comes out, reusing the register); line 10 adds; lines 11–12 store to c[7]; and RET reports the thread finished. Launch this with 2 blocks of 4 threads and the eight copies each pick a distinct i \in \{0,\dots,7\} — the whole vector is covered exactly once, with no thread ever mentioning any other.

An assembler in a screenful

A 16-bit fixed-format ISA is so regular that the assembler is barely a program: shift the opcode up twelve, OR the fields in. Here it is, encoding the kernel and then disassembling it back — the round trip is the proof the encoding loses nothing:

Twenty-six bytes of machine code. That is the entire program our GPU will spend the next four lessons learning to execute — first in one core, then dispatched across several, then through a realistic memory system, and finally end to end with every cycle accounted for.