The layout is routed, the clock tree is balanced,
So before the click comes signoff: a gauntlet of final exams, each run with paranoid, foundry-blessed tools, each of which must come back clean. This lesson walks the gauntlet — DRC, LVS, extraction, corner timing, power — then the late-surgery world of ECOs, and finally the moment itself: tape-out.
DRC — design-rule checking — asks whether the drawn geometry can be manufactured at all. The foundry publishes a rule deck: minimum wire widths, minimum spacings between shapes on each layer, via enclosure margins, metal-density windows (each region of each layer must be neither too empty nor too full, or polishing goes wrong)… At an advanced node the deck holds thousands of rules, many of them multi-shape and context-dependent, and the checker grinds over billions of polygons to verify every one. A single violation — two wires 1 nm too close — is a shape the fab cannot print reliably. Signoff DRC must be zero violations.
LVS — layout versus schematic — asks a different question: is the drawn silicon the circuit we meant? The tool extracts a netlist of transistors and connections from the geometry alone, then proves it equivalent to the golden netlist. A router glitch that shorted two nets, a power connection left dangling, a cell placed but never wired — LVS catches the difference between "printable" and "correct". DRC-clean but LVS-dirty means you would manufacture, flawlessly, the wrong chip.
Every earlier timing run used estimated wire delays. Now the wires are real, so parasitic extraction walks the final geometry and computes the actual resistance and capacitance of every net — coupling to neighbours included — and hands the result to signoff static timing analysis. Ordering matters and is absolute: extraction feeds STA; timing numbers computed without extracted parasitics are guesses.
And signoff STA does not run once. Silicon is not one chip — it is millions of chips, manufactured across process variation, run at different voltages, in freezing cars and hot servers. So the design is timed at PVT corners: combinations of Process (slow-slow SS, typical TT, fast-fast FF transistors), Voltage (nominal, minus tolerance, plus tolerance) and Temperature (say −40 °C, 25 °C, 125 °C). A corner is written like SS / 0.9 V / 125 °C — the pessimistic slow corner where setup checks usually bite — while hold checks tend to fail at fast, cold corners. With three values of each,
each analysed for both setup and hold, plus OCV margins (on-chip variation: even within one die, two "identical" gates differ, so paths are derated pessimistically). The chip must meet timing at every corner simultaneously — and alongside timing, power signoff checks electromigration (current density that would slowly erode wires) and IR drop across the whole grid one final time.
Signoff always finds something. With tape-out days away, nobody re-runs synthesis and placement — that would scramble the entire layout and reset months of closure. Instead the fix is an ECO, an engineering change order: a minimal, surgical netlist edit — swap this cell for a stronger drive, add one buffer here, reroute that net — applied incrementally so everything already clean stays untouched. Then the gauntlet re-runs.
The most prized kind is the metal-only ECO. Masks are made per layer; if a fix can be wired using only the metal layers — leaving every transistor where it is — then only the handful of metal masks must be re-made, at a small fraction of full mask-set cost. Even better, if the bug is found after silicon comes back, wafers that already finished the transistor layers can be salvaged: finish them with the new metal masks. But a metal-only fix needs transistors to wire to — which is why designers plant spare parts in advance (see the vignette below).
When every check is clean, the final layout database — in GDSII format, or its modern successor OASIS — is delivered to the foundry. The moment is called tape-out, a fossil of a name: in the 1970s the design really did leave the building as a reel of magnetic tape. Today it is an upload — followed, traditionally, by a party, because nothing anyone does from this point can change the masks.
That finality is the economics of the whole lesson. If a bug survives the gauntlet and escapes into silicon, the remedy is a respin: fix the design, buy new masks (millions of dollars), and wait months for the fab to run new wafers — while competitors ship and your market window closes. The mask cost is often the smaller loss; the calendar is the killer. A few weeks of paranoid signoff is the cheapest insurance in engineering.
Before tape-out, careful teams sprinkle a few thousand spare cells across the die — NANDs, NORs, inverters, flops — placed, powered, and connected to nothing. Pure dead weight? No: insurance. When a logic bug surfaces after tape-out (or after silicon returns), an ECO can often express the fix as "insert a gate here" — and if a suitable gate is already sitting nearby, the fix needs only wiring: a metal-only ECO, a handful of cheap metal masks instead of a full respin, and any part-processed wafers are saved too. It is the chip-design version of building a house with spare conduits in the walls: you hope never to need them, and the one time you do, they repay their cost ten-thousand-fold. The craft is in the sprinkling — spares are scattered uniformly, because nobody knows where the bug will be.
A design that meets timing at TT / nominal V / 25 °C has passed one exam out of dozens. Silicon ships to every corner: the die from the slow edge of the process lot, running at the low end of the voltage tolerance, inside a hot machine — and its fast, cold sibling too. The chip must pass all PVT combinations simultaneously, and here is the subtle trap: the corners disagree about which path is critical. The wire-dominated path that limits the SS corner may be comfortable at FF, where some gate-dominated path — or a hold check that typical analysis barely noticed — takes over as the problem. Fixing "the" critical path at one corner can even break another corner. Signoff is not one timing run with margin; it is the intersection of every corner's constraints, and only the full matrix of runs earns the word "closed".