Power Delivery and IR Drop

Here is a supply problem to respect: a modern server chip draws on the order of 100 amps at about 1 volt. One hundred amps — arc-welder territory — delivered not through copper bus bars but through micrometres-thin on-chip wiring, to a hundred million standard cells that each expect their VDD rail to sit rock-steady while they switch billions of times a second. The structure that pulls this off is the power delivery network (PDN), and its failure mode has a deceptively mild name: IR drop.

The PDN: a river system running downhill through the metal stack

Power enters the die at the package bumps — hundreds of solder balls across the chip's face, a large fraction of them dedicated purely to VDD and ground. From each bump the current descends a deliberate hierarchy:

top-metal grid — the thickest, lowest-resistance layers carry a coarse mesh of wide power straps across the whole die;
via stacks — towers of stacked vias drop the current down through the middle layers;
cell rails — finally the thin metal-1 VDD/VSS rails running along every standard-cell row, from which each cell drinks.

IR drop: Ohm's law collects its tax

Every wire in that hierarchy has resistance, and current through resistance costs voltage: V = I R. A cell far from the nearest bump, at the end of a long thin rail, sees not the nominal supply but the nominal minus the accumulated drop along its whole supply path. And a sagging supply is not a cosmetic problem: a gate at lower voltage switches more slowly. The cruellest part is where the sag strikes — drop is worst exactly where current is highest, i.e. in the busiest, most timing-critical regions. The chip fails timing precisely in the places it can least afford to.

Two flavours matter:

Static IR drop — the steady-state sag under average current: the baseline tax;
Dynamic (di/dt) drop — the transient dips when millions of cells switch in the same nanosecond (a clock edge, a unit waking up) and the demand spikes faster than the network can feed it. The local defence is the decoupling capacitor (decap): little charge reservoirs sprinkled through the layout that donate charge in the first instants of a spike, before the bumps can respond.

Slide the current draw up and watch the far end of a rail sag:

The curve's shape is worth reading: it droops quadratically, because near the bump the rail carries everyone's current, while each metre further along carries less — steepest sag first, then a flattening tail. The worst-served cell is the one at the far end.

Solve a rail yourself

// A 1-D resistive ladder: a rail fed at one end, n cells tapping current along it. // Segment j carries the current of all taps at or beyond j (KCL), so // V(k) = V0 − r · Σ_{j≤k} (current through segment j). const solveRail = (n: number, rPerSeg: number, iPerTap: number, v0: number) => { const volts: number[] = []; let v = v0; for (let k = 1; k <= n; k++) { const downstreamTaps = n - k + 1; // taps fed through segment k v -= rPerSeg * (downstreamTaps * iPerTap); volts.push(v); } return volts; }; const show = (label: string, volts: number[]) => { const sag = 1000 - volts[volts.length - 1]; console.log(label); console.log(" tap voltages (mV): " + volts.map((v) => v.toFixed(1)).join(" ")); console.log(` worst-case sag: ${sag.toFixed(1)} mV\n`); }; // 10 cells, 0.4 Ω per rail segment, 2 mA per cell, fed at 1000 mV. show("Baseline rail:", solveRail(10, 0.4, 2, 1000)); // Double the rail width → half the resistance per segment. show("Doubled rail width (r halved):", solveRail(10, 0.2, 2, 1000)); console.log("Doubling the metal width halved the drop — width is the PDN's currency.");

Electromigration: when current physically erodes the wire

IR drop is not the PDN's only failure mode. Push current density high enough and the electron wind literally blows metal atoms downstream — a slow erosion called electromigration (EM). Over months of operation, atoms pile up in one place (hillocks, which can short to neighbours) and vanish from another (voids, which eventually sever the wire). It is a wear-out mechanism: the chip works perfectly at birth and dies at three years old. The defences are blunt and effective: current-density limits per wire — hence minimum-width rules scaled to the current carried — enforced at signoff against the chip's target lifetime and temperature.

Physical design teams live in the PDN analysis tools' voltage heatmaps: die pictures coloured by worst-case supply voltage, hot spots marking regions where the grid needs more straps, more vias, more decap — or where the logic itself must spread out.

the PDN is a hierarchy: package bumps → thick top-metal grid → via stacks → thin cell rails;
IR drop (V = IR) makes distant, busy cells see a sagged supply — and lower voltage means slower gates, so drop turns into timing failure in exactly the busiest regions;
static drop is the steady tax; dynamic (di/dt) drop is the switching spike — fought locally with decoupling capacitors;
electromigration: sustained high current density transports metal atoms, voiding wires over years — countered by width rules tied to current and lifetime;
grid width is the currency: doubling a strap's width halves its drop.

It seems perverse: power lost in the delivery path is I^2R, so delivering a given wattage at higher voltage and lower current would waste far less — that is exactly why national grids run at hundreds of kilovolts. Chips are stuck on the other side of the bargain: transistor physics caps the core voltage around a volt (thin gate oxides simply break down above it, and dynamic power grows as V^2), so the amps have to be enormous. The system compromise is to convert late: the motherboard's voltage regulators sit as close to the socket as possible, stepping 12 V down to ~1 V in the final centimetres, and the package pours the resulting flood through hundreds of parallel bumps to keep each bump's share — and its I^2R loss — tolerable. The frontier is "integrated voltage regulation": doing that final conversion on the package or die itself, so the current only becomes huge for the last millimetre of its journey.

Here is the trap that has bitten real products: timing analysis and IR-drop analysis are different tools, traditionally run by different engineers — and each can pass while the silicon fails. Static timing analysis assumes some supply voltage per corner; the IR tool then shows that the busy core of the die actually sags 50 mV below that assumption. A path that met timing at the assumed voltage misses it at the voltage its gates really receive — the two reports are individually green and jointly fatal. Modern signoff therefore marries them: voltage-aware STA feeds each cell's analysed local supply voltage back into its delay lookup, timing the chip at the voltages it will genuinely experience. The general lesson generalises: failures love the seams between tools.