Packaging and Chiplets

The good dice from wafer sort are naked slivers of glass — fingernail-sized, fragile, with connection pads far too small and dense for any circuit board. The package is the chip's body: it fans the die's tiny pads out to solderable balls, feeds in amps of current, carries away a hundred-plus watts of heat, and armours the silicon against the world. For decades packaging was the unglamorous last step — "put it in a box". Then, quietly, the box became one of the most exciting places in computing: today's flagship processors are not one chip in a package but several dice engineered together, and the package is where the architecture happens.

From wire bond to flip-chip

The classic technique is wire bonding: glue the die face-up on a package substrate (a miniature multi-layer circuit board), then stitch hair-thin gold or copper wires, one by one, from pads along the die's edges down to the substrate. Cheap and still everywhere in low-cost chips — but the perimeter only holds a few hundred pads, and every signal and every milliamp must file through those long, inductive wires at the rim.

Flip-chip removes the bottleneck by using the whole face: cover the die's entire area with a grid of solder bumps, flip it upside down, and solder it face-down onto the substrate. Thousands of connections instead of hundreds, each a fraction of a millimetre long — and power can enter everywhere at once, straight down into the middle of the die, exactly what a grid drinking a hundred amps needs. The die's back now faces up, so a metal lid is pressed onto it through a layer of TIM (thermal interface material) to spread heat into the heatsink — with the perpetual worry that a few square millimetres of that die are hotspots burning many times the average power density.

The evolution, in cross-section

2.5D and 3D: silicon on silicon

A package substrate's wiring is coarse — its traces are tens of micrometres wide, so only so many can run between two chips. The breakthrough of 2.5D integration: set the dice side by side on a slab of silicon — an interposer — patterned with the same lithography as chips themselves. Now inter-die wires can be drawn at near on-chip density: thousands of them, connecting through micro-bumps (bumps shrunk to tens of micrometres). The interposer reaches the substrate below it through TSVs — through-silicon vias, conductive shafts drilled vertically through the silicon.

The flagship use is HBM (high-bandwidth memory): a tower of DRAM dice stacked and connected vertically by TSVs, parked a few millimetres from a GPU on the interposer, talking over an interface thousands of bits wide — bandwidth no circuit-board memory bus could dream of. Full 3D stacking goes further still: logic directly on logic, connected face-to-face by hybrid bonding — no bumps at all, copper pads on each die fused directly at micrometre pitch — putting, say, a cache die immediately on top of the cores that use it.

Chiplets: the yield exponential strikes back

Now recall the previous lesson's merciless formula, Y \approx e^{-AD}, and its corollary that doubling area squares the yield fraction. Read in reverse it is an offer: cut a big die into pieces and the exponential works for you. That is the chiplet strategy — split one enormous design into several small dice and reassemble them in the package:

Yield — four quarter-size dice each yield dramatically better than one giant, and a defect now scraps a quarter of the silicon, not all of it;
Mixed process nodes — compute chiplets on the newest, most expensive node; IO and analogue (which barely benefit from shrinking) on an older, cheaper one;
Reuse — one known-good IO die or memory die serves a whole product family; products scale by count (8, 16, 32 cores = 1, 2, 4 compute chiplets on one package).

The pieces talk over die-to-die links — short, wide, low-power interfaces crossing the interposer or substrate, now being standardised (UCIe is the emerging class) so chiplets from different vendors can plug together. The package has become architecture: partitioning a system into chiplets, choosing their interconnect, budgeting its latency and power, is now a co-design problem solved alongside the microarchitecture itself — not an afterthought at the loading dock.

// One 800 mm² monolith vs four 200 mm² chiplets, using the previous // lesson's yield model. PKG = extra packaging cost, ASSY = assembly yield. const waferCost = 12000; const PKG = 30; const ASSY = 0.97; const dicePerWafer = (a: number): number => Math.floor((Math.PI * 150 * 150) / a - (Math.PI * 300) / Math.sqrt(2 * a)); const goodDieCost = (a: number, d: number): number => waferCost / (dicePerWafer(a) * Math.exp(-(a / 100) * d)); console.log("D/cm² | monolithic 800 mm² | 4 × 200 mm² + pkg | winner"); for (const d of [0.0, 0.02, 0.05, 0.1, 0.2, 0.4]) { const mono = goodDieCost(800, d); const chip = (4 * goodDieCost(200, d) + PKG) / ASSY; console.log( d.toFixed(2).padStart(5) + " | $" + mono.toFixed(0).padStart(17) + " | $" + chip.toFixed(0).padStart(16) + " | " + (mono < chip ? "monolithic" : "chiplets"), ); } console.log(""); console.log("Only a defect-FREE fab favours the monolith. Real fabs have defects."); console.log(""); // But smaller systems flip the verdict — the overheads dominate: const d = 0.1; const mono100 = goodDieCost(100, d); const chip100 = (4 * goodDieCost(25, d) + PKG) / ASSY; console.log("100 mm² system at D=0.10: monolithic $" + mono100.toFixed(0) + " vs 4 × 25 mm² chiplets $" + chip100.toFixed(0)); console.log("Below a size threshold, monolithic still wins.");

wire bond connects only the die's perimeter; flip-chip uses the whole face — thousands of bumps and area-wide power delivery — with a lid and TIM carrying the heat away;
2.5D places dice on a silicon interposer: micro-bumps give near on-chip wiring density between dice, TSVs connect down to the substrate, and HBM stacks ride beside the logic;
3D stacking joins dice face-to-face (hybrid bonding) — logic on logic;
chiplets exploit the yield exponential in reverse: small dice yield far better, nodes can be mixed, and known-good dice are reused across products;
die-to-die links (UCIe-class) cost more energy per bit than on-die wires — package-level partitioning is a co-design decision, not a free lunch.

A data-centre GPU needs terabytes per second of memory bandwidth. Over a circuit board that is hopeless: board traces are so coarse that a few hundred wires is a luxurious bus, so the only lever left is signalling speed — burning watts per pin to sprint data down centimetres of copper. The interposer inverts the trade. With lithographically drawn wires, an HBM stack connects over thousands of wires a few millimetres long — each slow, quiet and cheap, together delivering staggering bandwidth at a fraction of the energy per bit. Distance is the tax on every bit moved; packaging is the art of shortening the trip. That is why the memory moved into the package — and it is the same logic, one level down, that pushes caches onto the die and, with 3D stacking, directly on top of the cores.

The cost table makes chiplets look like magic, so keep the bill in view. An on-die wire moves a bit for femtojoules; a die-to-die link over an interposer costs on the order of a picojoule per bit — roughly a thousand times more — plus added latency from crossing the boundary, and at terabytes per second those picojoules become real watts inside your power budget. The wires you can afford between chiplets, even on an interposer, are still far fewer than freely-drawn on-die wiring, so a bad partition strangles itself on its own seams. Packaging has its own yield too: bond four known-good dice and one botched attachment scraps them all — the assembly-yield divisor in the calculator above is doing real work. And every chiplet pays fixed overheads: interface controllers and PHYs on each die, interposer area, test cost per die. Run the small-system comparison again: below a size threshold, monolithic wins. Chiplets are the right tool when the yield exponential's savings outgrow the seam costs — a trade to be computed, not a fashion to be followed.