Clock Tree Synthesis

One signal on a chip has a job unlike any other. The clock must reach every flip-flop on the die — often a million of them — and arrive at all of them at the same instant. Not roughly the same instant: within a few picoseconds, across a piece of silicon a centimetre wide, through wires where a signal crawls at a fraction of the speed of light. No ordinary net faces anything like this. That is why, in the flow, the clock is not routed with the other nets at all: after placement and before signal routing, a dedicated step — clock tree synthesis (CTS) — builds the clock its own private distribution network, buffer by buffer.

Skew: the enemy, measured

Let t_i be the moment the clock edge arrives at flip-flop i (its arrival time, measured from the clock source; the overall source-to-sink delay is called the insertion delay). The skew is the spread:

\text{skew} = \max_i t_i - \min_i t_i.

Skew hurts twice, in opposite directions:

Setup: if the capturing flop's clock arrives early relative to the launching flop's, the data has less than a full period to travel — skew is subtracted straight off your timing budget. A 50 ps skew on a 500 ps cycle eats 10% of the chip's speed.
Hold: if the capturing flop's clock arrives late, the next data value can race through a short path and overwrite the current one before it is safely captured — a hold violation, which corrupts data outright.

CTS's core promise is skew held to a tiny bound. Its tools: a tree of identical clock buffers inserted level by level, wire lengths deliberately balanced so every root-to-sink path matches.

The H-tree: geometry does the balancing

The most elegant answer to skew is drawn, not computed. Start at the die's centre and draw an H: by symmetry, its four tips are at exactly equal wire length from the centre. Now make each tip the centre of a half-sized H: sixteen tips, still perfectly equidistant. Recurse. After L levels you have 4^L sinks, and every one of them is the same distance from the source — zero skew by construction:

Real chips cannot use a pure H-tree everywhere — flops are not arranged in neat powers of four, and macros punch holes in the pattern — so practical CTS builds buffered balanced trees: H-tree-like trunks feeding locally balanced branches, with buffer insertion equalising delays where geometry alone cannot. High-end CPUs go one step further: a clock mesh — a grid of wire driven from many points at once, shorting all the local arrival times together. Meshes achieve superbly low skew and tolerate variation, at the cost of substantial extra power — the mesh is essentially one giant capacitor toggling every cycle.

Compute a skew yourself

// A tiny clock tree: root → two buffers → four sinks. // Arrival at a sink = sum of buffer + wire delays along its path (ps). interface Sink { name: string; path: number[]; } const report = (label: string, sinks: Sink[]) => { const arrivals = sinks.map((s) => ({ name: s.name, t: s.path.reduce((a, b) => a + b, 0), })); for (const a of arrivals) console.log(` ${a.name}: ${a.t} ps`); const ts = arrivals.map((a) => a.t); const skew = Math.max(...ts) - Math.min(...ts); console.log(` → skew = ${skew} ps\n`); return skew; }; console.log("Before balancing (raw routed clock):"); report("before", [ { name: "FF0 (near) ", path: [60, 40] }, // short branch { name: "FF1 (near) ", path: [60, 55] }, { name: "FF2 (far) ", path: [60, 90, 70] }, // long branch { name: "FF3 (far) ", path: [60, 90, 95] }, ]); console.log("After CTS (buffers added to pad the short paths):"); report("after", [ { name: "FF0 (near) ", path: [60, 40, 118] }, // padding buffer inserted { name: "FF1 (near) ", path: [60, 55, 105] }, { name: "FF2 (far) ", path: [60, 90, 70] }, { name: "FF3 (far) ", path: [60, 90, 95] }, ]); console.log("Note the fix: CTS SLOWED the fast paths to match the slow ones."); console.log("Insertion delay grew — but the spread (skew) is what matters.");

Notice what balancing did: it made the fast paths slower. Insertion delay — the total source-to-sink latency — got worse; skew got better. That trade is the whole business of CTS, and it is a good trade, because flops only ever compare arrival times against each other.

The tree is also a power hog — and a tool

The clock net switches every cycle, everywhere — it is routinely 20–40% of a chip's dynamic power. This is exactly why clock gating (switching off the clock to idle blocks) is so effective, and the gating cells physically live inside the tree built by CTS: shutting a gate high in the tree stills an entire subtree of buffers and flops below it.

One more twist separates the masters from the apprentices: skew can be a tool. Useful skew deliberately delivers the clock slightly late to a flop whose incoming logic path is too slow — borrowing time from the (faster) next stage. CTS honours these intentional offsets while crushing all the unintentional ones.

skew = max − min clock arrival across the flops; it eats setup margin and causes hold failures — the two dangers point in opposite directions;
the H-tree equalises path lengths by recursive geometry (4^L sinks after L levels, all equidistant); practical CTS builds buffered balanced trees on the same principle;
clock meshes buy the lowest skew and variation-tolerance at a heavy power cost — the CPU-class option;
balancing works by slowing the fast paths: insertion delay rises so that the spread shrinks;
useful skew is deliberate, engineered skew that lends time to slow paths;
CTS runs after placement, before signal routing — and the clock-gating cells live inside the tree it builds.

The ordering is forced from both sides. CTS cannot run before placement because the tree's entire job is to reach the flops wherever they physically sit — no positions, no tree. And it must run before signal routing because the clock is the most timing-critical net on the chip: it gets first pick of the routing resources (typically the mid-stack layers, wide and shielded), and every data net then routes around it. There is a subtler reason too: once the tree exists, every flop's real clock arrival time is known, so the timing engine can stop assuming an ideal zero-skew clock and start using actual arrival times — from this point on, the design is being timed as the silicon will actually behave. That switch, from "ideal clock" to "propagated clock", is one of the flow's rites of passage.

Every designer's first instinct when timing fails: relax the clock. For a setup violation this works — a longer period gives the data more time. But a hold violation caused by skew is a race between the new data racing through a short path and the same edge arriving late at the capturing flop. Both contestants are launched by the same edge; the clock period appears nowhere in the inequality. Slow the clock to 1 Hz and the race plays out identically — hold is clock-frequency-independent. A chip with a real hold violation on a functional path is not "slow silicon you can down-bin"; it is dead at any speed — which is the scariest sentence in the back-end, and why hold margins are checked with extra paranoia and fixed by inserting delay into the offending short paths before tape-out.